Intel CONTROLLERS 413808 - Manual (Page 449)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 449
SRAM DMA Unit (SDMA)—Intel
®
413808 and 413812
5.4.4 LocalToHost Byte Count Register - L2H_BCR
The LocalToHost Byte Count Register (L2H_BCR) represents the byte count associated
with data to be moved. Note for internal architecture reasons the byte count must be
entered in two locations within this register.
Table 302. LocalToHost Byte Count Register - L2H_BCR
Bit Default Description
31:29 000
2
Reserved. Must be written as zero.
28:16 00000H
Byte Count Register (BCR)
This field specifies the length in bytes that is for the data to be transferred. The maximum transfer count
value is 4096 bytes (1000H). This field is CLEARED by a hardware or software reset.
15:13 000
2
Reserved. Must be written as zero.
12:00 000H
Byte Count Register (BCR)
This field specifies the length in bytes that is for the data to be transferred. The maximum transfer count
value is 4096 bytes (1000H). This field is CLEARED by a hardware or software reset. This must be
written the same as bits 28:16, otherwise unpredictable results occur.
Note: It is required that the byte count be written to both the upper and lower parts of this register (bits 28:16 and bits 12:00).
Failure to put the byte count in both locations renders unpredictable results.
Coprocessor
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Intel XScale ® Microarchitecture internal bus address offset
18218H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible