Intel CONTROLLERS 413808 - Manual (Page 285)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 285
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.14 Multi-Function Support
The 4138xx supports only one function, either ATU (TPER mode) or TPMI (IOC mode).
3.14.1 PCI Express Interface Control Parameters
The following registers are located in the configuration space header and extended
space and provide control of the PCI Express Interface. The effect of each bit is detailed
below.
Table 138. PCI Express Interface Control Parameters Usage (Sheet 1 of 2)
a
Register Name Register Bits Description Usage
ATU Command Register - ATUCMD
Bit 8 - SERR# Enable Each function can independently control this bit.
Bit 6 - Parity Error Response
The Parity Error Response bit from each function is
logically ORed and then fed to the PCI Interface. This
implies that Parity Error Response is globally enabled
when only one of the functions enables Parity Error
Response.
Bit 4 - MWI Enable Not applicable.
Bit 2 - Bus Master Enable Each function can independently control this bit.
Bit 1 - Memory Enable Each function can independently control this bit.
Bit 0 - I/O Enable Each function can independently control this bit.
ATU BIST Register - ATUBISTR Entire Register Each Function can independently control this register
PCI Express Device Control
Register - PE_DCTL
Bit[14:12] -
Max_Read_Request_Size
Use smallest programmed value when functions have
different values.
Bit[11] - Enable No Snoop Each Function can independently control this bit.
Bit[10] - Aux Power PM Enable Not applicable.
Bit[9] - Phantom Functions Enable Not applicable.
Bit[8] - Extended Tag Field Enable Not applicable.
Bit[7:5] - Max_Payload_Size
Use smallest programmed value when functions have
different values.
Bit[4] - Enable Relaxed Ordering Each Function can independently control this bit.
Bit[3] - Unsupported Request
Reporting Enable
Each function can independently control this bit.
Bit[2] - Fatal Error Reporting
Enable
Each function can independently control this bit.
Bit[1] - Non- Fatal Error Reporting
Enable
Each function can independently control this bit.
Bit[0] - Correctable Error
Reporting Enable
Each function can independently control this bit.
PCI Express Link Control Register
PE_LCTL
Bit[7] - Extended Sync
The bit from each function is logically ORed and then
fed to the PCI-E Interface.
Bit[6] - Common Clock
Configuration
Each function can independently control this bit.
Bit[5] - Retrain Link Applicable to Root Complex only.
Bit[4] - Link Disable Applicable to Root Complex only.
Bit[3] - Read Completion
Boundary (RCB) Control
Applicable to Root Complex only.
Bit[1:0] - Active State PM Control Inactive state when one of the functions is
programmed as inactive.