Intel CONTROLLERS 413808 - Manual (Page 57)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 57
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
Figure 5 shows an example of inbound address detection.
The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is
bitwise ANDed with the associated inbound limit register. When the result matches the
base register (and upper base address matches upper PCI address in case of DACs),
the inbound PCI address is detected as being within the inbound translation window
and is claimed by the ATU.
Note: By default, the first 8 Kbytes of the ATU inbound address translation window 0 are
reserved for the Messaging Unit. See Chapter 4.0, “Messaging Unit” .
Once the transaction is claimed, the address must be translated from a PCI address to
a 36-bit internal bus address. In case of DACs upper 32-bits of the address is simply
discarded and only the lower 32-bits are used during address translation. The algorithm
is:
The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed
with the bitwise inverse of the limit register. This result is bitwise ORed with the ATU
Translate Value, which is then ORed with the 4-bit ATU Upper Translate Value left
shifted by 32; the result is the 36-bit internal bus address. This translation mechanism
is used for all inbound memory read and write commands excluding inbound
configuration read and writes. Inbound configuration cycle translation is described in
Section 2.2.1.4, “Inbound Configuration Cycle Translation” on page 64 .
In the PCI mode for inbound memory transactions, the only burst order supported is
Linear Incrementing. For any other burst order, the ATU signals a Disconnect after the
first data phase. The PCI-X supports linear incrementing only, and hence the above
situation is never encountered in the PCI-X mode.
Figure 5. Inbound Address Detection
PCI Address
Space
Base_Register
Base_Register + Value of Limit_Register
Inbound
Translation
Window
Address is claimed
Address is not claimed
Address is not claimed
B6322-01
Equation 2. Inbound Translation
Intel ® 413808 and 413812 I/O Controllers Internal Bus Address = ((PCI_Address[31:0] &
~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]) | (ATU_Upper_Translate Value_Register[3:0]
<< 32).