Intel CONTROLLERS 413808 - Manual (Page 70)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
70 Order Number: 317805-001US
ATU has four 4 Gbyte outbound memory translation windows and one 64 Kbyte
outbound I/O translation window. By default, Outbound Memory Window 0
(OUMBAR0), Outbound Memory Window 1 (OUMBAR1), Outbound Memory Window 2
(OUMBAR2), and Outbound Memory Window 3 (OUMBAR3) reside in 4 Gbyte memory
sections 1, 2, 3, and 4, respectively. The default location of the 64 KByte outbound I/O
window range is from 0.FFFB.0000H to 0.FFFB.FFFFH. The following registers are used
to specify the five 4 Gbyte windows for claiming Outbound Memory transactions:
• Outbound Upper Memory Base Address Register 0 (OUMBAR0)
— Default Value equal to 01H.
• Outbound Upper Memory Base Address Register 1 (OUMBAR1)
— Default Value equal to 02H.
• Outbound Upper Memory Base Address Register 2 (OUMBAR2)
— Default Value equal to 03H.
• Outbound Upper Memory Base Address Register 3 (OUMBAR3)
— Default Value equal to 04H.
• Outbound I/O Base Address Register (OIOBAR)
— Default Value equal to 0FFF B000H
An internal bus cycle with an address within one outbound window initiates a read or
write cycle on the PCI bus. The PCI cycle type depends on which translation window the
local bus cycle “hits”. The read or write decision is based on the internal bus cycle type.
ATU has windows dedicated to the following outbound PCI/PCI-X transaction types:
• Memory reads and Memory writes - Memory Window
• I/O reads and writes - I/O Window
Table 5. Internal Bus-to-PCI Command Translation for Memory Windows
Internal Bus Command Conventional PCI Command PCI-X Command
Write a
a. The internal bus request does not cross a QWORD address boundary.
Memory Write Memory Write
Write b
b. The internal bus request does cross a QWORD address boundary
Memory Write and Invalidate c (DMA)
Memory Write (Memory Window 0-3)
c. The ATU converts Write to Memory Write and Invalidate when the following four conditions are met, otherwise
the Write is converted to a Memory Write:
1.) Memory Write and Invalidate transactions are enabled in the “ATU Command Register - ATUCMD” .
2.) The Cache Line size is set to 8 or 16 DWORDS in the “ATU Cacheline Size Register - ATUCLSR” .
3.) Starting address of the Outbound PCI bus request is aligned to the cache line size.
4.) Byte count intended for the Outbound PCI bus request is a multiple of the cache line size.
Memory Write Block (DMA)
Memory Write (Memory Window 0-3)
Read d
d. The internal bus request does not cross a DWORD address boundary.
Memory Read Memory Read DWORD
Read e
e. The internal bus request does cross a DWORD address boundary
Memory Read Multiple Memory Read Block
Table 6. Internal Bus-to-PCI Command Translation for I/O Window
Internal Bus Command
a
a. User should designate memory region containing I/O Window as non-cacheable and non-bufferable from Intel
XScale ® processor. This insures all load/stores to I/O Window are of DWORD quantities. In the event that the
user inadvertently issues a read to the I/O Window which crosses a DWORD address boundary, the ATU target
aborts the transaction. Only bytes 3:0 are relevant dependent on the Byte Enables.
Conventional PCI Command PCI-X Command
Write I/O Write I/O Write
Read I/O Read I/O Read