Intel CONTROLLERS 413808 - Manual (Page 28)

Intel
®
413808 and 413812—Contents
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
28 Order Number: 317805-001US
217 PCI Express Advanced Error Header Log - ADVERR_LOG1 ............................................361
218 PCI Express Advanced Error Header Log - ADVERR_LOG2 ............................................361
219 PCI Express Advanced Error Header Log - ADVERR_LOG3 ............................................362
220 Root Error Command Register - RERR_CMD ...............................................................362
221 Root Error Status Register - RERR_SR.......................................................................363
222 Error Source Identification Register RERR_ID .............................................................364
223 Device Serial Number Capability - DSN_CAP...............................................................364
224 Device Serial Number Lower DW Register - DSN_LDW.................................................365
225 Device Serial Number Upper DW Register - DSN_UDW ................................................365
226 PCI Express Advisory Error Control Register PIE_AEC ..................................................366
227 Power Budgeting Enhanced Capability Header - PWRBGT_CAPID...................................367
228 Power Budgeting Data Select Register - PWRBGT_DSEL...............................................367
229 Power Budgeting Data Register - PWRBGT_DATA........................................................368
230 Power Budgeting Capability Register - PWRBGT_CAP...................................................369
231 Power Budgeting Information Registers[0:23]—PWRBGT_INFO[0:23]............................370
232 Outbound I/O Base Address Register - OIOBAR ..........................................................371
233 Outbound I/O Window Translate Value Register - OIOWTVR.........................................372
234 Outbound Upper Memory Window Base Address Register 0 - OUMBAR0 ........................373
235 Outbound Upper 32-bit Memory Window Translate Value Register 0- OUMWTVR0............374
236 Outbound Upper Memory Window Base Address Register 1 - OUMBAR1 ........................375
237 Outbound Upper 32-bit Memory Window Translate Value Register 1- OUMWTVR1............376
238 Outbound Upper Memory Window Base Address Register 2- OUMBAR2 .........................377
239 Outbound Upper 32-bit Memory Window Translate Value Register 2- OUMWTVR2............378
240 Outbound Upper Memory Window Base Address Register 3 - OUMBAR3 ........................379
241 Outbound Upper 32-bit Memory Window Translate Value Register 3- OUMWTVR3............380
242 Outbound Configuration Cycle Address Register - OCCAR.............................................381
243 Outbound Configuration Cycle Data Register - OCCDR .................................................382
244 Outbound Configuration Cycle Function Number - OCCFN.............................................383
245 Inbound Vendor Defined Message Header Register0 - IVMHR0......................................384
246 Inbound Vendor Defined Message Header Register 1 - IVMHR1.....................................385
247 Inbound Vendor Defined Message Header Register 2 - IVMHR2.....................................386
248 Inbound Vendor Defined Message Header Register 3 - IVMHR3.....................................387
249 Inbound Vendor Defined Message Payload Register - IVMPR.........................................387
250 Outbound Vendor Defined Message Header Register0 - OVMHR0...................................388
251 Outbound Vendor Defined Message Header Register 1 - OVMHR1..................................389
252 Outbound Vendor Defined Message Header Register 2 - OVMHR2..................................390
253 Outbound Vendor Defined Message Header Register 3 - OVMHR3..................................390
254 Outbound Vendor Defined Message Payload Register - OVMPR......................................391
255 PCI Interface Error Control and Status Register - PIE_CSR ...........................................392
256 PCI Interface Error Status - PIE_STS.........................................................................393
257 PCI Interface Error Mask - PIE_MSK..........................................................................394
258 PCI Interface Error Header Log - PIE_LOG0................................................................395
259 PCI Interface Error Header Log 1 - PIE_LOG1.............................................................395
260 PCI Interface Error Header Log 2 - PIE_LOG2.............................................................396
261 PCI Interface Error Header Log - PIE_LOG3................................................................396
262 PCI Interface Error Descriptor Log - PIE_DLOG...........................................................397
263 ATU Reset Control Register - ATURCR .......................................................................397
264 MU Summary.........................................................................................................401
265 Message Unit Registers ...........................................................................................411
266 Inbound Message Register - IMRx.............................................................................412
267 Outbound Message Register - OMRx..........................................................................412
268 Inbound Doorbell Register - IDR...............................................................................413
269 Inbound Interrupt Status Register - IISR ...................................................................414
270 Inbound Interrupt Mask Register - IIMR.....................................................................415
271 Outbound Doorbell Register - ODR............................................................................416