Intel CONTROLLERS 413808 - Manual (Page 289)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 289
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17 Register Definitions
Every PCI device implements its own separate configuration address space and
configuration registers. The PCI Express Specification extends the configuration space
to 4096 bytes as compared to 256 bytes allowed by PCI Local Bus Specification,
Revision 2.3. The ATU configuration space is divided into a PCI 2.3 compatible region
consisting of the first 256 bytes and an extended PCI express configuration space
region consisting of the remaining space. The PCI 2.3 compatible space provides
support for legacy operating systems. The first 64 bytes must adhere to a predefined
header format.
Figure 32 defines the header format. Table 141 shows the PCI configuration registers,
listed by internal bus address offset. Table 141 shows the entire ATU configuration
space (including header and extended registers) and the corresponding section that
describes each register. Note that all configuration read and write transactions is
accepted on the internal bus as 32-bit transactions. Refer to Chapter 19.0, “Peripheral
Registers” .
The ATU is programmed via a Type 0 configuration command on the PCI interface. See
Section 3.3.1.5, “Inbound Configuration Cycle Translation (ID Routed)” on page 242 .
ATU configuration space is function number zero of the 4138xx single-function PCI
device.
Beyond the required 64 byte header format, ATU configuration space implements
extended register space in support of the units functionality. Refer to the PCI Express
Base Specification, Revision 1.0a for details on accessing and programming
configuration register space.
Figure 32. ATU Interface Configuration Header Format
ATU Device ID Vendor ID 00H
Status Command 04H
ATU Class Code Revision ID 08H
ATUBISTR Header Type Latency Timer Cacheline Size 0CH
Inbound ATU Base Address 0 10H
Inbound ATU Upper Base Address 0 14H
Inbound ATU Base Address 1 18H
Inbound ATU Upper Base Address 1 1CH
Inbound ATU Base Address 2 20H
Inbound ATU Upper Base Address 2 24H
Reserved 28H
ATU Subsystem ID ATU Subsystem Vendor ID 2CH
Expansion ROM Base Address 30H
Reserved Capabilities Pointer 34H
Reserved 38H
Maximum Latency Minimum Grant Interrupt Pin Interrupt Line 3CH