Intel CONTROLLERS 413808 - Manual (Page 114)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
114 Order Number: 317805-001US
2.7.8 SERR# Assertion and Detection
The ATU is capable of reporting error conditions through the use of the SERR# output.
The following conditions may result in the assertion of SERR# by the ATU:
• An uncorrectable address error (or an uncorrectable attribute error when operating
in the PCI-X mode) is detected by the ATU PCI interface (see Section 2.7.1,
“Uncorrectable Address and Uncorrectable Attribute Errors on the PCI Interface” on
page 95 for details).
• A Master Data Parity Error is recorded in the ATUSR while operating in the PCI-X
mode (see Section 2.7.3, “Uncorrectable Data Errors on the PCI Interface” on
page 97 for details).
• An outbound MSI write transaction is either signaled a Master-Abort or a
Target-Abort by the target.
• An inbound write transaction is master aborted on the internal bus (see Section
2.7.9.1, “Master Abort on the Internal Bus” on page 115 for details).
• The SERR# Manual Assertion bit in the ATUCR has been set and the SERR# Enable
bit is set in the ATUCMD.
Note that the SERR# manual assertion bits must be cleared manually before they can
be set again resulting in SERR# asserted. Refer to Section 2.14.40, “ATU Configuration
Register - ATUCR” on page 177 for details.
The following actions with the given constraints are performed by the ATU when
SERR# is asserted by the PCI interface:
• Set the SERR# Asserted bit in the ATUSR.
• When the ATU SERR# Asserted Interrupt Mask bit in the ATUIMR is clear, set the
SERR# Asserted bit in the ATUISR. When set, no action.
• When SERR# is asserted and the ATU SERR# Detected interrupt enable is set in
the ATUCR, set the SERR# Detected bit in the ATUISR. When clear, no action.
The following actions with the given constraints are performed by the ATU when
SERR# is detected by the PCI interface:
• When SERR# is detected and the ATU SERR# Detected interrupt enable is set in
the ATUCR, set the SERR# Detected bit in the ATUISR. When clear, no action.
Note: Whenever the ATU asserts SERR# , both the asserted and detected status bits may be
set in the corresponding ISR. To mask an interrupt to the core when the ATU asserts
SERR# , the SERR# asserted mask bit must be set and the SERR# detected interrupt
enable bit must be clear.