Intel CONTROLLERS 413808 - Manual (Page 672)

Intel ® 413808 and 413812—UARTs
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
672 Order Number: 317805-001US
13.4.4 UART x Interrupt Identification Register
The IIR register is read to determine the type and source of UART interrupts. To be
16550 compatible, the lower 4 bits (0-3) of the IIR register are priority encoded as
shown in Table 451, “Interrupt Identification Register Decode” on page 673 . When two
or more interrupts represented by bits (0-3) occur, only the interrupt with the highest
priority is displayed. The upper 4 bits, (4-7) are not priority encoded. These bits
asserts/deasserts independently of the lower 4 bits.
Bit 0 (nIP) is used to indicate the existence of an interrupt in the priority encoded bits
(0-3) of the IIR register. A low signal on this bit indicates an encoded interrupt is
pending. When this bit is high, no encoded interrupt is pending, regardless of the state
of the other 3 bits. IP# has no effect or association with the upper bits four bits (4-7)
which assert/deassert independently of IP#.
In order to minimize software overhead during data character transfers, the UART
prioritizes interrupts into four levels (listed in Table 451, “Interrupt Identification
Register Decode” on page 673 ) and records these in the Interrupt Identification
register. The Interrupt Identification register (IIR) stores information indicating that a
prioritized interrupt is pending and the source of that interrupt.
Table 450. UART x Interrupt Identification Register - (UxIIR)
Bit Default Description
31:8 00 0000h Reserved
7:6 00
2
FIFO Mode Enable Status (FIFOES[1:0]):
00 = Non-FIFO mode is selected
01 = Reserved
10 = Reserved
11 = FIFO mode is selected (TRFIFOE = 1)
5 0
2
Reserved
4 0
2
Autobaud Lock (ABL)
0 = Autobaud circuitry has not programmed Divisor Latch registers (DLL/DLH)
1 = Divisor Latch registers (DLL/DLH) programmed by autobaud circuitry
3 0
2
Time Out Detected (TOD):
0 = No time out interrupt is pending
1 = Time out interrupt is pending. (FIFO mode only)
2:1 0
2
Interrupt Source Encoded (IID[1:0]): indicates a Modem Status Interrupt when the
IP# bit is low. When IP# bit is high, there is no Interrupt.
00 = Modem Status (CTS, DSR, RI, DCD modem signals changed state)
01 = Transmit FIFO requests data
10 = Received Data Available
11 = Receive error (Overrun, parity, framing, break, FIFO error)
0 1
2
Interrupt Pending (IP#):
0 = Interrupt is pending. (Active low)
1 = No interrupt is pending
PC
I
IO
P
A
tt
ri
b
u
te
s
A
tt
ri
b
u
te
s
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
ro
na
ro
na
rv
na
ro
na
ro
na
ro
na
ro
na
ro
na
Unit #
01
Intel XScale ® Core internal bus address
+2308H (DLAB=x)
+2348H (DLAB=x)
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible