3 boundary-scan register, 4 bypass register, 5 device identification register – Intel CONTROLLERS 413808 User Manual

Page 792: Figure 123. iop device id register, Table 521. iop device id register settings, 123 iop device id register, 520 iop device id register field definitions, 521 iop device id register settings, Idcode, Test-logic-reset

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Intel

®

413808 and 413812—Test Logic Unit and Testability

Intel

®

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

792

Order Number: 317805-001US

18.2.3.3 Boundary-Scan Register

Boundary-Scan Register is a set of serial-shiftable register cells, connected between

each system pin and on-chip system logic. (Power, ground and TAP pins excluded.) This

forms a single shift register between TDI and TDO of all the system pins.
This is the most extensive, complex register in the test circuitry. This register allows

testing of circuitry external to the component (e.g. board interconnect) in addition to

device system logic. It permits the system signals (into and out of the system logic) to

be sampled and examined without causing interference with the normal operation of

the system logic. Further definition, rules, and specifics of the Boundary-Scan Register

can be found in the

IEEE Std, 1149.1-2001, Chapter 10

.

18.2.3.4 Bypass Register

The Bypass Register is a single-bit, serial-shift register connecting

TDI

and

TDO

when

the Bypass instruction is in effect. This allows rapid movement of test data to and from

other board components, since this register provides the shortest path between

TDI

and

TDO

. This path can be selected when no test operation is being performed. While

the Bypass Register is selected, data is transferred from

TDI

to

TDO

without inversion.

18.2.3.5 Device Identification Register

The Device Identification (ID) Register is a 32-bit register used for storing the

manufacturer identification, part number, and the version of the processor. It is a

dedicated part of the test logic and is not usable in system functionality.
The identification register is selected only by the

IDCODE

instruction. When the

Test-Logic-Reset

state of the TAP controller is entered, the IDCODE instruction is

automatically loaded into the instruction register. The generic format of the register is

discussed in chapter 11 of the IEEE 1149.1 Standard.

Figure 123. IOP Device ID Register

Note:

See Intel

®

413808 and 413812 I/O Controllers

Table 520. IOP Device ID Register Field Definitions

Field

Value

Definition

Version

0000 = A-0 Step

Indicates stepping changes.

Manufacturer ID 0000 0001 0011 (Indicates Intel)

Manufacturer ID assigned by IEEE.

Table 521. IOP Device ID Register Settings

Description

Device ID

Complete ID (Hex)

Complete ID (Binary)

4138xx A-0 (ATU-E)

0x3361

0011001101100001b

4138xx A-0 (ATU-XE)

0x3369

0011001101101001b

28

24

20

4

0

16

12

8

1

1

0

0

1

0

0

0

0

0

0

0

Manufacturer ID

Part Number

Version

Model

Gen

Product Type

VCC

1

1

0

0

1

0

0

1

0

0

1

X

X

0

1

0

B6314-01

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