Interrupt controller unit—intel, Bit default description – Intel CONTROLLERS 413808 User Manual

Page 597

Advertising
background image

Intel

®

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

597

Interrupt Controller Unit—Intel

®

413808 and 413812

04

0

2

IMU Interrupt Pending.

0 = Masked

1 = Not Masked

03

0

2

ATU-E Error Interrupt Pending.

0 = Masked

1 = Not Masked

02

0

2

ATU-E Configuration Register Write Interrupt Pending.

0 = Masked

1 = Not Masked

01

0

2

ATU-E/Start BIST Interrupt Pending.

0 = Masked

1 = Not Masked

00

0

2

I

2

C Bus Interface 2 Interrupt Pending.

0 = Masked

1 = Not Masked

Table 394. Interrupt Control Register 3 — INTCTL3 (Sheet 2 of 2)

Bit

Default

Description

Memory

Coprocessor

Attributes

Attributes

28

24

20

16

12

8

4

0

31

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Intel XScale

®

processor Coprocessor address

CP6, Page 4, Register 3

Advertising