Intel CONTROLLERS 413808 - Manual (Page 629)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 629
Timers—Intel ® 413808 and 413812
11.1.2 Watch Dog Timer Operation
The Watch Dog Timer (WDT) is a 32-bit down counter that can be used to reset the
Internal Bus and the Intel XScale
®
processor or generate an interrupt when software
gets stuck in an infinite loop. Refer to Section 426, “Watch Dog Timer Setup Register —
WDTSR” on page 639 for setting up the Watchdog timer. A reset of the Internal Bus
also results in the M_RST# output to be asserted which can be used to reset the
system or as an external indicator of the WDT expiration.
Following
P_RST# assertion, the WDT is disabled.
The software can enable the WDT by using coprocessor instructions (that is, MCR or
LDC) to write the value 1E1E 1E1EH followed by the value E1E1 E1E1H to the WDT
Control register. When enabled, the WDT is initialized with FFFF FFFFH and begin to
decrement towards 0000 0000H.
The software is required periodically to write the WDT initialization sequence (the value
1E1E 1E1EH followed by the value E1E1 E1E1H) to the WDT Control register in order to
reset the timer value to FFFF FFFFH. For a 300 MHz internal bus, this means that the
sequence must be written approximately every fourteen seconds.
Note: The WDT always runs at Intel XScale
®
processor speed without any prescaling.
When the software fails to reinitialize the WDT prior to the timer value transitioning to
zero, an Internal Bus Reset is generated. This reinitializes all Internal Bus peripherals
and the Intel XScale
®
processor.
Once enabled, the WDT can be disabled by writing the value 1F1F 1F1FH followed by
the value F1F1 F1F1H to the WDT Control register. The WDT can be enabled again by
writing the value 1E1E 1E1EH followed by the value E1E1 E1E1H to the WDT Control
register.