Intel CONTROLLERS 413808 - Manual (Page 469)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 469
SGPIO Unit—Intel
®
413808 and 413812
6.5 SGPIO Unit Mode of Operations
Each SGPIO unit on 4138xx can be programmed to support the following modes:
• Direct LED
• SGPIO
4138xx provides eight configurable pins per SGPIO unit to accommodate SGPIO mode.
When the SGPIO unit is set up to operate in Direct LED mode by clearing bit[0] of
Table 321, “SGPIO Interface Control Register x - SGICRx” on page 475 , all eight pins
provide direct LED support. For example, all the output signals are directly driven to the
corresponding pins.
When the SGPIO unit is set up to operate in SGPIO mode by setting bit[0] of the
Table 321, “SGPIO Interface Control Register x - SGICRx” on page 475 , four of eight
pins provide the SGPIO bus.
Figure 52 shows how selected output signals are routed into a multiplexer block and
how outputs of the multiplexer block are routed to the shift register and direct LED
signals. The multiplexer block provides the ability to select how drive output signals are
ordered before being driven to the shift register and to direct LED signals. Note, all
three output signals of each drive are selected simultaneously. In direct LED mode,
programming the multiplexer allows any four drive output signals to be selected and
driven on direct LED pins. The programmable feature of SGPIO allows for either SGPIO
unit to support any number of drive combinations. For example, the eight drives
supported on 4138xx can be distributed between the two SGPIO units.
Note: Only output signals OD0 and OD1 of the lower four outputs of the multiplexer block
(Output[3:0]) are routed to direct LED signals. For example, each SGPIO unit can only
support up to eight direct LED output signals: four Protocol Engine activity and four
Protocol Engine Status signals.
Figure 52. Output Signal Routing
OD0
Multiplexer Block Drive Position Selector
24x(8-to-1)
Note 1: Only OD0 and OD1 of the lower four sets of the Multiplexer Block outputs are driven to the Direct LED pins.
.
Input 7 Input 0
Bit 23 Bit 22 Bit 21 Bit 1 Bit 0 Bit 2
OD1
Control bits from SGSDRx
Shift Register
OD1 OD2 OD0 OD1 OD2 OD 0
Input 3
Bit 10 Bit 9 Bit 11
OD1 OD2 OD0
Input 4
Bit 13 Bit 12 Bit 14
OD 1 OD2
Output 0
OD1 OD0 OD2
Output 3
OD1 OD0 OD2
Output 4
OD1 OD0 OD2
Output 7
OD1 OD0 OD 2
To SDataOut
Bit 23 Bit 22 Bit 21 Bit 1 Bit 0 Bit 2 Bit 10 Bit 9 Bit 11 Bit 13 Bit 12 Bit 14
OD0
OD0
OD1
To Direct
LED Signals
Bit 23 Bit 22 Bit 21 Bit 1 Bit 0 Bit 2 Bit 10 Bit 9 Bit 11 Bit 13 Bit 12 Bit 14
Drive 7 Drive 0 Drive 3 Drive 4
Note 2: The Multiplexer Block only allows steering an entire Input X set to an Output Y set.
B6351-01