Intel CONTROLLERS 413808 - Manual (Page 150)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
150 Order Number: 317805-001US
03 0
2
Interrupt Status - This bit reflects the state of the interrupt in the 4138xx ATU function. Only when the
Interrupt Disable bit in the ATUCMD is a 0 and this Interrupt Status bit is a 1, are any of the 4138xx’s
INT[A:D]# signals asserted by the ATU function.
Note: Setting the Interrupt Disable bit to a 1 in (bit 10 of ATUCMD) has no effect on the state of this
bit.
02:00 000
2
Reserved
Table 32. ATU Status Register - ATUSR (Sheet 2 of 2)
Bit Default Description
PCI
IOP
Attributes
Attributes
15 12 8 4 0
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
ro
ro
ro
ro
rc
rc
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rv
rv
rv
rv
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+006H