9 atu cacheline size register - atuclsr, Table 148. atu cacheline size register - atuclsr, 10 atu latency timer register - atult – Intel CONTROLLERS 413808 User Manual
Page 301: Table 149. atu latency timer register - atult, 10atu latency timer register - atult, 148 atu cacheline size register - atuclsr, 149 atu latency timer register - atult, Address translation unit (pci express)—intel, Bit default description
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
301
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.9
ATU Cacheline Size Register - ATUCLSR
Cacheline Size Register bit definitions adhere to PCI Local Bus Specification,
Revision 2.3. This register is programmed with the system cacheline size in DWORDs
(32-bit words). Cacheline Size is restricted to either 0, 8 or 16 DWORDs; the ATU
interprets any other value as “0”.
3.17.10 ATU Latency Timer Register - ATULT
ATU Latency Timer Register does not apply to PCI Express.
Table 148. ATU Cacheline Size Register - ATUCLSR
Bit
Default
Description
07:00
00H
ATU Cacheline Size - specifies the system cacheline size in DWORDs.
Note:
This field is read-write for legacy compatibility purposes but has no impact on any PCI Express
device functionality.
PCI
IOP
Attributes
Attributes
7
4
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+00CH
Table 149. ATU Latency Timer Register - ATULT
Bit
Default
Description
07:00
00H
Programmable Latency Timer - The latency timer does not apply to PCI Express.
Hard-wired 0.
PCI
IOP
Attributes
Attributes
7
4
0
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+00DH