Intel CONTROLLERS 413808 - Manual (Page 774)

Intel ® 413808 and 413812—Clocking and Reset
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
774 Order Number: 317805-001US
17.2.8 Internal Bus Reset
This reset can be initiated through:
• The coordinated reset bits in the MU Section 4.7.4, “Inbound Interrupt Status
Register - IISR” on page 414 .
• The watchdog timer as described in Section 11.1.2, “Watch Dog Timer Operation”
on page 629 .
This function resets the Intel XScale
®
processor and all units on the internal bus, while
preserving the PCI Configuration Registers.
Software must quiesce all PCI bus traffic before initiating the Internal Bus Reset.
1. Disable the ATU from either claiming or initiating new transactions by clearing the
Bus Master Enable and the Memory Enable in the ATU Command Register.
2. Monitor the Inbound Read Transaction Queue Status, the Outbound Read
Transaction Queue Status, and in PCI Express mode, the Link Layer Retry Buffer
Status in the PCSR.
3. When the Inbound Read Transaction queue, the Outbound Read Transaction queue,
and the Link Layer Retry Buffer are empty, software writes to the Coordinated
Reset bit to initiate the Internal Bus Reset.
The Intel XScale
®
processor may or may not be held in reset, depending on the default
value of the Core Processor Reset bit as described in Section 17.2.7, “Intel XScale®
Processor Reset Mechanism” .