Intel CONTROLLERS 413808 - Manual (Page 7)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 7
Contents—Intel
®
413808 and 413812
2.14.63HS_CNTRL - Hot-Swap Control/Status Register ........................................ 202
2.14.64Inbound ATU Base Address Register 3 - IABAR3 ....................................... 204
2.14.65Inbound ATU Upper Base Address Register 3 - IAUBAR3............................ 205
2.14.66Inbound ATU Limit Register 3 - IALR3 ..................................................... 206
2.14.67Inbound ATU Translate Value Register 3 - IATVR3 .................................... 207
2.14.68Inbound ATU Upper Translate Value Register 3 - IAUTVR3 ......................... 207
2.14.69Outbound I/O Base Address Register - OIOBAR ........................................ 208
2.14.70Outbound I/O Window Translate Value Register - OIOWTVR....................... 209
2.14.71Outbound Upper Memory Window Base Address Register 0 - OUMBAR0 ....... 210
2.14.72Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
211
2.14.73Outbound Upper Memory Window Base Address Register 1 - OUMBAR1 ....... 212
2.14.74Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
213
2.14.75Outbound Upper Memory Window Base Address Register 2 - OUMBAR2 ....... 214
2.14.76Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2
215
2.14.77Outbound Upper Memory Window Base Address Register 3 - OUMBAR3 ....... 216
2.14.78Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3
217
2.14.79Outbound Configuration Cycle Address Register - OCCAR........................... 218
2.14.80Outbound Configuration Cycle Data Register - OCCDR............................... 219
2.14.81Outbound Configuration Cycle Function Number - OCCFN .......................... 219
2.14.82PCI Interface Error Control and Status Register - PIECSR........................... 220
2.14.83PCI Interface Error Address Register - PCIEAR.......................................... 221
2.14.84PCI Interface Error Upper Address Register - PCIEUAR .............................. 222
2.14.85PCI Interface Error Context Address Register — PCIECAR .......................... 223
2.14.86Internal Arbiter Control Register - IACR................................................... 224
2.14.87Multi-Transaction Timer - MTT................................................................ 225
2.14.88PCIX RCOMP Control Register — PRCR .................................................... 226
2.14.89PCIX Pad ODT Drive Strength Manual Override Values Registers — PPODSMOVR
227
2.14.90PCIX PAD DRIVE STRENGTH Manual Override Values ........ Register (3.3 V/1.5 V
Switch Supply Voltage) — PPDSMOVR3.3_1.5228
2.14.91PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated
Supply Voltage) — PPDSMOVR3.3229
3.0 Address Translation Unit (PCI Express)........................................................................ 230
3.1 Overview ....................................................................................................... 230
3.2 PCI Express Link Characteristics........................................................................ 233
3.3 ATU Address Translation .................................................................................. 234
3.3.1 Inbound Transactions ........................................................................... 237
3.3.1.1 Inbound Address Translation .................................................... 237
3.3.1.2 Inbound Memory Write Transaction ........................................... 240
3.3.1.3 Inbound Memory Read Transaction ........................................... 241
3.3.1.4 Inbound I/O Cycle Translation .................................................. 242
3.3.1.5 Inbound Configuration Cycle Translation (ID Routed)................... 242
3.3.1.6 Inbound Vendor_Defined Message Transactions .......................... 243
3.3.2 Outbound Transactions ......................................................................... 244
3.3.2.1 Outbound Address Translation - Internal Bus Transactions............ 245
3.3.2.2 Outbound Address Translation Windows..................................... 246
3.3.2.3 Outbound DMA Transactions..................................................... 250
3.3.2.4 Outbound Function Number...................................................... 250
3.3.3 Outbound Write Transaction .................................................................. 251
3.3.4 Outbound Read Transaction................................................................... 252
3.3.5 Outbound Configuration Cycle Translation................................................ 253