Intel CONTROLLERS 413808 - Manual (Page 472)

Intel
®
413808 and 413812—SGPIO Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
472 Order Number: 317805-001US
6.5.1 Pin Multiplexing
All S_ACT[7:0] and S_STAT[7:0] pins are multiplexed. Note that an SGPIO interface is
a 4-pin interface. SGPIO unit 0 uses pins S_ACT[3:0] and S_STAT]3:0] for SGPIO
signaling and direct LED controls, whereas SGPIO unit 1 uses pins S_ACT[7:4] and
S_STAT[7:4] for SGPIO signaling and direct LED controls. Table 318 and Figure 322
show how the SGPIO unit 0 signals are multiplexed. Table 319 on page 473 and
Figure 54 on page 473 show how the SGPIO unit 1 signals are multiplexed. Bit 0 of
Table 321, “SGPIO Interface Control Register x - SGICRx” on page 475 is used to select
between the SGPIO signals and the direct LED signals, and by default bit 0 selects the
SGPIO signals. The direct LED signals and the TXRATE signals are selected based on
product types.
Note: TXRATEx[y] signals are valid signals only for product types that support fibre channel
ports. The multiplexers are controlled per the product type. For example, a 4138xx that
supports only SAS ports has the multiplexers selecting S_ACT[x] and S_STAT[x]
signals.
Note: TXRATEx[y] signals are valid signals only for product types that support fibre-channel
ports. Multiplexers are controlled per product type. For example, a 4138xx that
Table 318. SGPIO Unit 0 Pin Multiplexing
Activity Pin Shared Pin Status Pin Shared Pin
S_ACT[0] SCLOCK[0] S_STAT[0] SLOAD[0]
S_ACT[1] TXRATE0[0] S_STAT[1] TXRATE0[1]
S_ACT[2] SDATAIN[0] S_STAT[2] SDATAOUT[0]
S_ACT[3] TXRATE2[0] S_STAT[3] TXRATE2[1]
Note: Protocol Engine activity and status signal pairs are not connected to corresponding SGPIO unit drive numbers.
Figure 53. Intel
®
413808 and 413812 I/O Controllers in TPER Mode SGPIO Unit 0 Pin
Mapping
S_ACT [2] / SDATAIN [0]
S_ STAT[2] / SDATAOUT[0]
S_ACT[3] / TXRATE 2[0]
S_STAT[3] / TXRATE2 [1]
S_ACT[0] / SCLOCK[0]
S_ STAT[0] / SLOAD[0]
S_ ACT [1] / TXRATE 0[0]
S_STAT[1] / TXRATE0[1]
TXRATE 2[0]
TXRATE 2 [1]
TXRATE0[0]
TXRATE0[1]
SDATAOUT
SDATAIN
SLOAD
SCLOCK
STAT[3]
STAT[2]
STAT[1]
STAT[0]
ACT [3]
ACT [0]
ACT [1]
ACT [2]
Control bit 0 of the
SGICCR0 Register
S_ STAT[5]
ACT[3]
SDATAIN
SDATAOUT
STAT[0]
SLOAD
ACT[2]
SCLOCK
ACT[0]
STAT[1]
ACT [1]
STAT[2]
STAT[3]
S_ACT [5]
S_ STAT[7]
S_ACT [7]
S_ STAT[1]
S_ACT [1]
S_ STAT[3]
S_ACT [3]
S_ STAT[0]
S_ACT [0]
S_ STAT[2]
S_ACT [2]
S_ STAT[4]
S_ACT [4]
S_ STAT[6]
S_ACT [6]
SGPIO Unit 0
Dr0_ACT_in
Dr0_STAT_in
Dr1_ACT_in
Dr1_STAT_in
Dr2_ACT_in
Dr2_STAT_in
Dr3_ACT_in
Dr3_STAT_in
Dr4_ACT_in
Dr4_STAT_in
Dr5_ACT_in
Dr5_STAT_in
Dr6_ACT_in
Dr6_STAT_in
Dr7_ACT_in
Dr7_STAT_in
Dr2_ STAT_out
Dr1_ ACT_out
Dr0_ STAT_out
Dr0_ ACT_out
Dr3_ ACT_out
Dr2_ ACT_out
Dr1_ STAT_out
Dr3_ STAT_out
B6352-01