Intel CONTROLLERS 413808 - Manual (Page 95)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 95
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.1 Uncorrectable Address and Uncorrectable Attribute Errors on
the PCI Interface
The ATUs must detect and report uncorrectable address and attribute (PCI-X mode
only) errors for transactions on the PCI bus. When an uncorrectable address or
attribute error occurs on the PCI interface of the ATU, the 4138xx performs the
following actions based on the constraints specified:
• In Conventional mode, when the Parity Error Response bit in ATUCMD is set, the
ATU ignores (Master-Abort) the transaction by not asserting DEVSEL# . When clear,
the transaction proceeds normally.
• In PCI-X mode, when the Parity Error Response bit in ATUCMD is set, the ATU
completes the transaction on the PCI bus as when no error had occurred, but the
request or completion is not forwarded to the internal bus. When clear, the
transaction proceeds normally.
• Assert SERR# when the SERR# Enable bit and the Parity Error Response bit in the
ATUCMD are set. When the ATU asserts SERR#, additional actions is taken:
— Set the SERR# Asserted bit in the ATUSR
— When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set
the SERR# Asserted bit in the ATUISR. When set, no action.
— When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR (see Section
2.14.40, “ATU Configuration Register - ATUCR” on page 177 ) is set, set the
SERR# Detected bit in the ATUISR. When clear, no action.
• Set the Detected Uncorrectable Address or Attribute Error bit in PCSR (PCI
Configuration and Status Register).
• Set the Detected Parity Error bit in the ATUSR. When the ATU sets the Detected
Parity Error bit, additional actions is taken:
— When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear,
set the Detected Parity Error bit in the ATUISR. When set, no action.
• For PCI-X Mode 2, update the “ECC Control and Status Register - ECCCSR” on
page 195 , the “ECC First Address Register - ECCFAR” on page 198 , the “ECC
Second Address Register - ECCSAR” on page 199 , and the “ECC Attribute Register -
ECCAR” on page 200 for the transaction
Note: The Detected Parity Error bit with its’ associated interrupt along with the Detected
Uncorrectable Address or Attribute Error bit provides software with the ability to
distinguish between an Uncorrectable Address or Attribute error versus an
Uncorrectable Data Error during a Detected Parity error interrupt.