Intel CONTROLLERS 413808 - Manual (Page 708)

Intel ® 413808 and 413812—I 2 C Bus Interface Units
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
708 Order Number: 317805-001US
14.4 Slave Mode Programming Examples
14.4.1 Initialize Unit
1. Write ISAR: Set slave address
2. Write ICR: Enable all interrupts, set Unit Enable
14.4.2 Write 1 Byte as a Slave
1. Wait for Slave Address Detected interrupt.
Read ISR: Slave Address Detected (set), Unit Busy (set), R/W# bit (1), Ack/Nack
(Clear - Ack)
2. Write IDBR: Load data byte to transfer
3. Write ICR: Set Transfer Byte bit
4. Wait for IDBR Transmit Empty interrupt.
Read ISR: IDBR Transmit Empty (set), Ack/Nack (set - indicates last byte write),
R/W# bit (0)
5. Clear interrupt by clearing the IDBR Transmit Empty Interrupt bit.
6. Wait for interrupt.
Read ISR: Unit Busy (clear), Slave STOP Detected (set)
7. Clear interrupt by clearing Slave STOP Detected Interrupt bit.
14.4.3 Read 2 Bytes as a Slave
1. Wait for Slave Address Detected interrupt.
Read ISR: Slave Address Detected (set), Unit busy (set), R/W# bit (0)
2. Read byte 1 on I
2
C bus
Write ICR: Set Transfer Byte bit to initiate the transfer
3. Wait for interrupt.
Read ISR: IDBR Receive Full (set), Ack/Nack (clear), R/W# bit (0)
Clear interrupt by clearing IDBR Receive Full bit.
Read IDBR: To get the data.
4. Read byte 2 on I
2
C bus
Write ICR: Set Transfer Byte bit to initiate the transfer
5. Wait for interrupt.
Read ISR: IDBR Receive Full (set), Ack/Nack (clear), R/W# bit (0)
Clear interrupt by clearing IDBR Receive Full bit.
Read IDBR: To get the data.
Write ICR: Set Transfer Byte bit (to release I
2
C bus allowing next transfer)
6. Wait for interrupt.
Read ISR: Unit busy (clear), Slave STOP Detected (set)
Clear interrupt by clearing Slave STOP Detected bit.