118 pci interface error header log - pie_log0, 119 pci interface error header log 1 - pie_log1, 118pci interface error header log - pie_log0 – Intel CONTROLLERS 413808 User Manual

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413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

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395

Address Translation Unit (PCI Express)—Intel

413808 and 413812

3.17.118 PCI Interface Error Header Log - PIE_LOG0

Transaction header log for PCI interface errors.

3.17.119 PCI Interface Error Header Log 1 - PIE_LOG1

Transaction header log for PCI interface errors.

Table 258. PCI Interface Error Header Log - PIE_LOG0

Bit

Default

Description

31:0

1st DWord of the Header for the PCI Express packet in error.

Once an error is logged in this register, it remains locked for further error logging until the time the

software clears the status bit that cause the header log i.e. the error pointer is rearmed to log again.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+38CH

Table 259. PCI Interface Error Header Log 1 - PIE_LOG1

Bit