Intel CONTROLLERS 413808 - Manual (Page 32)

Intel
®
413808 and 413812—Contents
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
32 Order Number: 317805-001US
437 SMBus Controller ADDR2 Register — SM_ADDR2 ........................................................656
438 SMBus Controller ADDR1 Register Number — SM_ADDR1 ............................................657
439 SMBus Controller ADDR0 Register Number — SM_ADDR0 ............................................657
440 SMBus Controller Data Register — SM_DATA..............................................................658
441 SMBus Controller Status Register — SM_STS .............................................................658
442 UART Signal Descriptions.........................................................................................661
443 Divisor Values for Typical Baud Rates........................................................................666
444 UART Register Addresses as Offsets of a Base ............................................................668
445 UART Unit Registers................................................................................................668
446 UART Register MMR Addresses .................................................................................669
447 UART x Receive Buffer Register - (UxRBR) .................................................................670
448 UART x Transmit Holding Register - (UxTHR)..............................................................670
449 UART x Interrupt Enable Register - (UxIER) ...............................................................671
450 UART x Interrupt Identification Register - (UxIIR).......................................................672
451 Interrupt Identification Register Decode ....................................................................673
452 UART x FIFO Control Register - (UxFCR)....................................................................674
453 UART x Line Control Register - (UxLCR).....................................................................676
454 UART x Modem Control Register - (UxMCR)................................................................678
455 UART x Line Status Register - (UxLSR)......................................................................680
456 UART x Modem Status Register ................................................................................683
457 UART x Modem Status Register - (UxMSR).................................................................683
458 UART x Scratchpad Register - (UxSCR)......................................................................684
459 UART x Divisor Latch Low Register - (UxDLL) .............................................................685
460 UART x Divisor Latch High Register - (UxDLH)............................................................685
461 UART x FIFO Occupancy Register - (UxFOR)...............................................................686
462 UART x Auto-Baud Control Register - (UxABR)............................................................687
463 UART x Auto-Baud Count Register - (UxACR) .............................................................688
464 I
2
C Bus Definitions .................................................................................................690
465 Modes of Operation.................................................................................................694
466 START and STOP Bit Definitions................................................................................695
467 Master Transactions................................................................................................702
468 Slave Transactions..................................................................................................705
469 General Call Address Second Byte Definitions.............................................................707
470 I
2
C Register Summary ............................................................................................714
471 I
2
C Control Register x — ICRx..................................................................................715
472 I
2
C Status Register x — ISRx ...................................................................................717
473 I
2
C Slave Address Register x — ISARx.......................................................................719
474 I
2
C Data Buffer Register x — IDBRx..........................................................................720
475 I
2
C Bus Monitor Register x — IBMRx .........................................................................721
476 I
2
C Manual Bus Control Register x — IMBCRx.............................................................722
477 General Purpose I/O Registers Addresses...................................................................724
478 GPIO Output Enable Register — GPOE .......................................................................725
479 GPIO Input Data Register — GPID ............................................................................726
480 GPIO Output Data Register — GPOD .........................................................................728
481 Simple Time Based Counting of Events Example .........................................................733
482 Hardware Event Based Event Counting Example .........................................................735
483 Hardware Event Based Event Counting Example .........................................................737
484 Queue Depth Histogram Example .............................................................................738
485 Head of Queue Histogram Example ...........................................................................739
486 PMON Internal Bus Memory Mapped Register Range Offsets........................................745
487 PMON Register Summaries .....................................................................................745
488 PMON Feature Enable Register - PMON EN................................................................746
489 PMON Status Register - PMON STAT ........................................................................746
490 PMON Internal Bus Memory Mapped Register Range Offsets........................................747
491 PMON Register Summaries .....................................................................................748