Intel, Bit default description – Intel CONTROLLERS 413808 User Manual

Page 682

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Intel

413808 and 413812—UARTs

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

682

Order Number: 317805-001US

Parity Error (PE): Indicates that the received data character does not have the
correct even or odd parity, as selected by the even parity select bit. The PE is set (1)
upon detection of a parity error and is cleared (0) when the processor reads the Line
Status register. In FIFO mode, PE shows a parity error for the character at the bottom
of the FIFO, not the most recently received character.

0 = No Parity error.
1 = Parity error has occurred.

Overflow Error (OE): In non-FIFO mode, OE indicates that data in the Receiver
Buffer register was not read before the next character was received, the new
character is lost.

In FIFO mode, OE indicates that all 64 bytes of the FIFO are full and the most
recently received byte has been discarded. The OE indicator is set (1) upon detection
of an overflow condition and reset when the processor reads the Line Status register.

0 = No overflow error. Data has not been lost.
1 = Overflow error. Receive data has been lost.

Data Ready (DR): Set to a logic 1 when a complete incoming character has been
received and transferred into the receiver buffer register or the FIFO. In non-FIFO
mode, DR is reset to 0 when the receive buffer is read. In FIFO mode, DR is reset to
a logic 0 when the FIFO is empty (last character has been read from RBR) or the
RESETRF bit is set in FCR.

0 = No data has been received.
1 = Data is available in RBR or the FIFO.

Table 455. UART x Line Status Register - (UxLSR) (Sheet 3 of 3)

Bit

Default

Description

Unit #

Intel XScale

Core internal bus address

+2314H (DLAB=x)

+2354H (DLAB=x)

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

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