Intel CONTROLLERS 413808 - Manual (Page 60)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
60 Order Number: 317805-001US
Data flow for the inbound write transaction on the internal bus is summarized as:
• The ATU internal bus master requests the internal bus when IWADQ has at least
one entry with associated data in the IWQ.
• When the internal bus is granted, the internal bus master interface initiates the
write transaction by driving the translated address onto the internal bus. For details
on inbound address translation, see Section 2.2, “ATU Address Translation” on
page 53 .
• When an internal bus target does not claim write transaction, a master abort
condition is signaled on the internal bus. The current transaction is flushed from the
queue and SERR# may be asserted on the PCI interface.
• The ATU initiator interface attempts a 128-bit wide transfer on the internal bus.
When the target that claims the request does not support 128-bit wide transfers, a
64-bit wide transfer is used. Transfers of use internal bus byte enables to mask the
bytes not written in each data phase. Write data is transferred from the IWQ to the
internal bus when data is available and the internal bus interface retains internal
bus ownership. Refer to Chapter 7.0, “System Controller (SC) and Internal Bus
Bridge” for details of internal bus operation.
• The internal bus interface stops transferring data from the current transaction to
the internal bus when one of the following conditions becomes true:
— The data from the current transaction has completed (satisfaction of byte
count). An initiator termination is performed and the bus returns to idle.
— A Master Abort is signaled on the internal bus. SERR# may be asserted on the
PCI bus. Data is flushed from the IWQ.