Intel CONTROLLERS 413808 - Manual (Page 566)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
566 Order Number: 317805-001US
10.2 Theory of Operation
10.2.1 Interrupt Controller Unit
The 4138xx Interrupt Controller Unit (ICU) provides the ability to generate interrupts to
both the Intel XScale
®
processor and the PCI interrupt pins.
In addition to the internal peripherals, external devices may also generate interrupts to
the Intel XScale
®
processor. External devices can generate interrupts via the
XINT[15:0]# pin and the HPI# pin. The Interrupt Controller Unit provides the ability
to direct PCI interrupts as outputs ( P_INT[D:A]# ) for the PCI-X interface when acting
as an endpoint.
The Interrupt Controller Unit has two functions:
• Internal Peripheral Interrupt Control
• External Interrupt Generation
The internal peripheral interrupt control mechanism consolidates a number of interrupt
sources for a given peripheral into a single interrupt driven to the Intel XScale
®
processor. High performance data movement associated interrupts are fully
demultiplexed into the ICU, however. In order to provide the executing software with
the knowledge of interrupt source, coprocessor mapped status registers describe the
source of the active interrupts and the vectors to interrupt handlers for the highest
priority active sources. All of the peripheral interrupts are individually enabled from the
respective peripheral control registers.
In addition to the interrupts supported by the ICU, the 4138xx provides one
non-maskable interrupt per Intel XScale
®
processor. Non-Maskable Interrupt 0
( NMI0# ) — is driven to Intel XScale
®
processor 0, and Non-Maskable Interrupt 1
( NMI1# ) — is driven to Intel XScale
®
processor 1. These pins are falling edge
triggered input signals. NMI0# or NMI1# causes an imprecise data abort which is the
second highest priority exception (higher than even an FIQ exception). Refer to
Table 376, “Exception Priorities And Vectors” on page 568 . Since the data abort is
imprecise it could potentially occur while in the middle of an abort handler, making it
impossible to resume normal operation. When this an error needs to be recoverable the
system should route these errors to either IRQ or FIQ by using the external interrupt
input pins XINT[0:15]# .