Intel CONTROLLERS 413808 - Manual (Page 18)

Intel
®
413808 and 413812—Contents
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
18 Order Number: 317805-001US
14.4 Slave Mode Programming Examples ...................................................................708
14.4.1 Initialize Unit .......................................................................................708
14.4.2 Write 1 Byte as a Slave .........................................................................708
14.4.3 Read 2 Bytes as a Slave ........................................................................708
14.5 Master Programming Examples..........................................................................709
14.5.1 Initialize Unit .......................................................................................709
14.5.2 Write 1 Byte as a Master........................................................................709
14.5.3 Read 1 Byte as a Master........................................................................709
14.5.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master ........................710
14.5.5 Read 2 Bytes as a Master — Send STOP Using the Abort............................711
14.6 Glitch Suppression Logic...................................................................................712
14.7 Reset Conditions..............................................................................................713
14.8 Register Definitions..........................................................................................714
14.8.1 I
2
C Control Register x — ICRx ................................................................715
14.8.2 I
2
C Status Register x — ISRx .................................................................717
14.8.3 I
2
C Slave Address Register x — ISARx.....................................................719
14.8.4 I
2
C Data Buffer Register x — IDBRx ........................................................720
14.8.5 I
2
C Bus Monitor Register x — IBMRx .......................................................721
14.8.6 I
2
C Manual Bus Control Register x — IMBCRx ...........................................722
15.0 General Purpose I/O Unit ...........................................................................................723
15.1 General Purpose Input Output Support ...............................................................723
15.1.1 General Purpose Inputs .........................................................................723
15.1.2 General Purpose Outputs .......................................................................723
15.1.3 Reset Initialization of General Purpose I/O Function...................................723
15.2 Register Definitions..........................................................................................724
15.2.1 GPIO Output Enable Register — GPOE .....................................................725
15.2.2 GPIO Input Data Register — GPID...........................................................726
15.2.3 GPIO Output Data Register — GPOD........................................................728
16.0 PMON Unit ..............................................................................................................729
16.1 PMON Counters ..............................................................................................729
16.2 Overview........................................................................................................729
16.2.1 Clock Counter Control ...........................................................................730
16.3 Definitions ......................................................................................................731
16.4 Data Collection................................................................................................732
16.4.1 Time Based Sampling............................................................................732
16.4.2 Hardware Event Based Control ...............................................................734
16.4.3 Incrementing By More Than 1.................................................................736
16.4.4 Queue Analysis.....................................................................................737
16.5 Non-Register-Based Interfaces ..........................................................................743
16.5.1 Events Input Port..................................................................................743
16.5.2 Output Signals .....................................................................................743
16.5.2.1 Indicator Output .....................................................................744
16.5.2.2 Interrupt Output .....................................................................744
16.5.3 Internal Bus Addresses..........................................................................745
16.5.4 PMON Feature Enable Register - PMON EN ..............................................746
16.5.5 PMON Status Register - PMON STAT.......................................................746
16.5.6 PMON Memory Mapped Registers...........................................................747
16.5.6.1 PMON Command Register 0-7 - PMON _CMD[0:7] ......................749
16.5.6.2 PMON Event Register 0-7 - PMON _EVR[0:7] .............................753
16.5.6.3 PMON Status Register 0-7 - PMON _STS[0:7] ............................754
16.5.6.4 PMON Data Register 0-7 - PMON _DATA[0:7].............................756
16.5.7 PMON Events ......................................................................................757
16.5.7.1 Null Event ..............................................................................757
16.5.7.2 Clock Events...........................................................................758