Intel CONTROLLERS 413808 - Manual (Page 237)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 237
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.3.1 Inbound Transactions
Inbound transactions are received on the PCI Express receive port and forward to the
4138xx internal bus. This transactions include all requests for which the ATU is the
completer as well as completions for which the ATU was the initiator.
Inbound request transactions which target the ATU are translated and executed on the
4138xx internal bus. As a PCI Express completer, the ATU is capable of accepting all
memory, I/O, and configuration request. Additionally, as a PCI Express end-point, the
ATU would never request more memory read data than it can hold in its Inbound
Completion Data Queue.
Inbound memory write (and message) transactions have their headers entered into the
inbound posted header queue (IPHQ) and data entered into the inbound posted data
queue (IPDQ). The IPHQ/IPDQ pair are capable of holding up to 16 posted operations
up to the size of the data queue. Inbound configuration (or I/O) write transactions use
the inbound non posted header queue (INPHQ) and inbound non posted data queue
(INPDQ). The INPDQ has room for one configuration or I/O write at a time. Refer to
Section 3.8 for details of queue operation. Inbound read transaction (memory,
configuration, and I/O) have their header entered into the inbound non posted header
queue (INPHQ) and the data are returned to the PCI Express requester in the outbound
completion data queue (OCPLDQ). The INPQ is capable of holding up to 8 non posted
requests and any associated data.
Operation of the internal bus is defined in
Section 7.0, “System Controller (SC) and
Internal Bus Bridge” .PCI Express has three principal mechanisms for Transaction Layer
Packet (TLP) routing: address, ID, and implicit. The following sections describes how
the ATU routes and translates each type.
3.3.1.1 Inbound Address Translation
PCI Express utilizes both 32-bit and 64-bit address schemes via the 3DW and 4DW
headers. To prevent address aliasing, all devices must decode the entire address range.
All discussions in this section refer to 64-bit addressing. When the 3DW header is used
the upper 32-bits of address are assumed to be 0000_0000h.
The ATU allows external PCI Express requesters to directly access the internal bus via
address routed TLPs. These PCI Express requesters can read or write 4138xx
memory-mapped registers or 4138xx local memory space. The process of inbound
address translation involves two steps:
1. Address Detection.
— Verify the PCI address is within the address windows defined for the inbound
ATU.
— When the address is outside of the ATU address registers, the transaction is
terminated as an unsupported request (UR).
2. Address Translation.
— Translate the lower 32-bit PCI address to a 36-bit 4138xx internal bus address.
The ATU uses the following registers in inbound address window 0 translation:
• Section 3.17.13, “Inbound ATU Base Address Register 0 - IABAR0” on page 304
• Section 3.17.28, “Inbound ATU Limit Register 0 - IALR0” on page 318
• Section 3.17.29, “Inbound ATU Translate Value Register 0 - IATVR0” on page 319
• Section 3.17.30, “Inbound ATU Upper Translate Value Register 0 - IAUTVR0” on
page 319
The ATU uses the following registers in inbound address window 1 translation: