Intel CONTROLLERS 413808 - Manual (Page 595)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 595
Interrupt Controller Unit—Intel
®
413808 and 413812
10.7.11 Interrupt Control Register 2 — INTCTL2
The Interrupt Control register 2 is a 32-bit Coprocessor 6 control register used to
specify which of 32 interrupts are masked.
Table 393. Interrupt Control Register 2 — INTCTL2
Bit Default Description
31 0
2
SRAM Memory Controller Unit Error Interrupt Mask.
0 = Masked
1 = Not Masked
30 0
2
South Internal Bus Bridge Error Interrupt Mask.
0 = Masked
1 = Not Masked
29:14 0
2
Reserved.
13 0
2
SRAM DMA Error Interrupt Mask.
0 = Masked
1 = Not Masked
12 0
2
SRAM DMA Normal Interrupt Mask.
0 = Masked
1 = Not Masked
11:03 0
2
Reserved.
02 0
2
Reserved.
01 0
2
Reserved.
00 0
2
Reserved.
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 4, Register 2