Intel, Bit default description – Intel CONTROLLERS 413808 User Manual
Page 370
Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
370
Order Number: 317805-001US
3.17.91 Power Budgeting Information
Registers[0:23]—PWRBGT_INFO[0:23]
There are 24 power budgeting information registers that are used to report power
consumption information for power states as defined in the PCI Express Base
Specification, Revision 1.0a. These registers are reflected in the
based on the setting of the Data Select field in the
Budgeting Data Select Register - PWRBGT_DSEL
.
The lower 8 bits of the offset can be determined by shifting the Data Select value left
by 2 (i.e. multiply by 4). Currently the default values are all 0, this may change once
we get real power/thermal numbers for 4138xx.
Data
Select
PWRBGT_INFOx
Register
Offset
Data
Select PWRBGT_INFOx
Register
Offset
00h
0
+200H
0Ch
12
+230H
01h
1
+204H
0Dh
13
+234H
02h
2
+208H
0Eh
14
+238H
03h
3
+20CH
0Fh
15
+23CH
04h
4
+210H
10h
16
+240H
05h
5
+214H
11h
17
+244H
06h
6
+218H
12h
18
+248H
07h
7
+21CH
13h
19
+24CH
08h
8
+220H
14h
20
+250H
09h
9
+224H
15h
21
+254H
0Ah
10
+228H
16h
22
+258H
0Bh
11
+22CH
17h
23
+25CH
Table 231. Power Budgeting Information Registers[0:23]—PWRBGT_INFO[0:23]
Bit
Default
Description
31:21
000H
Preserved
20:0
00000H
“Power Budgeting Data Register - PWRBGT_DATA” on page 368
for format.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RZ = Reserved Zero
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+200 through +25FH