1 pbi control register - pbcr, Table 364. pbi control register - pbcr, 2 pbi status register - pbisr – Intel CONTROLLERS 413808 User Manual
Page 555: Table 365. pbi status register - pbisr, 1 pbi control register — pbcr, 2 pbi status register — pbisr, 364 pbi control register — pbcr, 365 pbi status register — pbisr, Pbi status register — pbisr” on, Table 364. pbi control register — pbcr
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
555
Peripheral Bus Interface Unit—Intel
®
413808 and 413812
9.3.1
PBI Control Register — PBCR
The PBI Control Register (PBCR) is responsible for enabling operation of PBI state
machines.
9.3.2
PBI Status Register — PBISR
The PBI Status Register (PBISR) allows software to determine the cause of any PBI
interrupts.
Table 364. PBI Control Register — PBCR
Bit
Default
Description
31:28
0H
Reserved.
27:24
0H
PBI Memory Window 1 Upper 4-bit address. These bits, with PBBAR1 form a 36-bit base address.
23:20
0H
Reserved.
19:16
0H
PBI Memory Window 0 Upper 4-bit address. These bits, with PBBAR0 form a 36-bit base address.
15:04
000H
Reserved.
03
0
2
Reserved.
02:01
00
Reserved (bit[2] reads as 1).
00
1
2
PBI Enable: When set, this bit enables the PBI unit bus interface
0 = Peripheral Bus Disabled
1 = Peripheral Bus Enabled.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale
®
processor Local Bus Address
Offset
+1580H
Table 365. PBI Status Register — PBISR
Bit
Default
Description
31:01
0
Reserved
00
0
2
Byte Count Out of Range Error — Indicates that the address and byte-count combination of a write
request claimed by the PBI was not legal. Write requests made to the PBI is only permitted to be within
a DWORD boundary. For example, when the address and byte-count combination spans a DWORD
boundary, the PBI signals an address error condition and set this bit.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rc
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale
®
processor Local Bus Address
Offset
+1584H