Intel CONTROLLERS 413808 - Manual (Page 389)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 389
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.111 Outbound Vendor Message Header Register 1 - OVMHR1
The Outbound Vendor Message Header Registers allow software to create a header that
is used for a Vendor_Defined Message TLP. The OVMHR0-3 registers must be
programmed prior to writing the Outbound Vendor Defined Message Payload Register -
OVMPR . A write to the OVMPR initiates the Vendor_Defined Message TLP. When the
payload length is 0, a write to the OVMPR is still required to initiate the TLP but the
data written is ignored.
Vendor_Defined message format is shown in
Figure 38
Table 251. Outbound Vendor Defined Message Header Register 1 - OVMHR1
Bit Default Description
31:24 00H Requester ID - Bus number. This value is copied from the Bus number field in the PCISR.
23:19 0_0000 Requester ID - Device Number. This value is copied from the Device number field in the PCISR
18:16 000 Requester ID - Function Number. This value is programmable.
15:8 00H Tag - The tag field is undefined for posted requests. Hardcoded to 0.
7:0 0111_1110
Message Code[7:0] - Indicates the type of message being generated. Valid encodings are:
0111_1110 Vendor_Defined Type 0
0111_1111 Vendor_Defined Type 1
Other codes may result in malformed packets.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rw
ro
rw
ro
rw
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+364H