Intel CONTROLLERS 413808 - Manual (Page 99)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 99
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.3.1.2 Split Response Termination
As an initiator, the ATU may encounter this error condition in PCI-X mode when the
target signals a Split Response Termination.
Parity errors occurring during Split Response Terminations of Read Requests by the ATU
are recorded, PERR# is asserted (when enabled) and SERR# is asserted (when
enabled). Specifically, the following actions with the given constraints are taken by the
ATU:
• PERR# is asserted two clocks cycles (three clock cycles when operating in the
PCI-X mode) following the Split Response Termination in which the parity error is
detected on the bus. This is only done when the Parity Error Response bit in the
ATUCMD is set. When the ATU asserts PERR# , additional actions are taken:
— The Master Parity Error bit in the ATUSR is set.
— When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear,
set the PCI Master Parity Error bit in the ATUISR. When set, no action.
— When the SERR# Enable bit in the ATUCMD is set, and the Uncorrectable Data
Error Recover Enable bit in the PCIXCMD register is clear, assert SERR# ,
otherwise no action. When the ATU asserts SERR#, additional actions are
taken:
Set the SERR# Asserted bit in the ATUSR.
When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set
the SERR# Asserted bit in the ATUISR. When set, no action.
When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set
the SERR# Detected bit in the ATUISR. When clear, no action
• The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit,
additional actions are taken:
— When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear,
set the Detected Parity Error bit in the ATUISR. When set, no action.
• For PCI-X Mode 2, update the “ECC Control and Status Register - ECCCSR” on
page 195 , the “ECC First Address Register - ECCFAR” on page 198 , the “ECC
Second Address Register - ECCSAR” on page 199 , and the “ECC Attribute Register -
ECCAR” on page 200 for the transaction.
The Outbound Read Request remains enqueued in the ATU since the completer is
initiating completion transactions that are associated with this request.