Intel CONTROLLERS 413808 - Manual (Page 24)

Intel
®
413808 and 413812—Contents
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
24 Order Number: 317805-001US
Tables
1 Intel
®
413808 and 413812 I/O Controllers in TPER Mode/Firmware Mapping ....................36
2 Documentation References ........................................................................................40
3 ATU Command Support.............................................................................................54
4 Outbound Address Translation Control.........................................................................68
5 Internal Bus-to-PCI Command Translation for Memory Windows .....................................70
6 Internal Bus-to-PCI Command Translation for I/O Window .............................................70
7 Compact PCI Hot-Swap .............................................................................................80
8 HS_FREQ Encoding ..................................................................................................81
9 Inbound Queues.......................................................................................................83
10 Inbound Read Prefetch Data Sizes ..............................................................................84
11 PCI to Internal Bus Command Translation for All Inbound Transactions............................85
12 Outbound Queues.....................................................................................................86
13 ATU Inbound Data Flow Ordering Rules .......................................................................87
14 ATU Outbound Data Flow Ordering Rules .....................................................................88
15 Inbound Transaction Ordering Summary......................................................................90
16 Outbound Transaction Ordering Summary....................................................................91
17 Parity Generation .....................................................................................................92
18 ATU Error Reporting Summary - PCI Interface............................................................119
19 ATU Error Reporting Summary - Internal Bus Interface................................................124
20 PCI-X Interface Control Parameters Usage .................................................................130
21 PCI-X Host Interface Status Reporting Usage .............................................................131
22 CR_FREQ[1:0] Encoding........................................................................................133
23 Device Mode/Frequency Capability Reporting..............................................................134
24 PCI Bus Frequency Initialization................................................................................135
25 PCI-X Initialization Pattern.......................................................................................136
26 Address Translation Unit Registers............................................................................143
27 ATU Internal Bus Memory Mapped Register Range Offsets............................................146
28 PCI-X Pad Registers................................................................................................146
29 ATU Vendor ID Register - ATUVID.............................................................................147
30 ATU Device ID Register - ATUDID.............................................................................147
31 ATU Command Register - ATUCMD...........................................................................148
32 ATU Status Register - ATUSR ...................................................................................149
33 ATU Revision ID Register - ATURID...........................................................................151
34 ATU Class Code Register - ATUCCR ...........................................................................151
35 ATU Cacheline Size Register - ATUCLSR.....................................................................152
36 ATU Latency Timer Register - ATULT .........................................................................152
37 ATU Header Type Register - ATUHTR.........................................................................153
38 ATU BIST Register - ATUBISTR.................................................................................154
39 Inbound ATU Base Address Register 0 - IABAR0 .........................................................155
40 Inbound ATU Upper Base Address Register 0 - IAUBAR0 ..............................................156
41 Inbound ATU Base Address Register 1 - IABAR1 .........................................................157
42 Inbound ATU Upper Base Address Register 1 - IAUBAR1 ..............................................158
43 Inbound ATU Base Address Register 2 - IABAR2 .........................................................159
44 Inbound ATU Upper Base Address Register 2 - IAUBAR2 ..............................................160
45 ATU Subsystem Vendor ID Register - ASVIR...............................................................161
46 ATU Subsystem ID Register - ASIR ...........................................................................161
47 Expansion ROM Base Address Register -ERBAR...........................................................162
48 ATU Capabilities Pointer Register - ATU_Cap_Ptr.........................................................163
49 Memory Block Size Read Response ...........................................................................164
50 ATU Base Registers and Associated Limit Registers .....................................................165
51 ATU Interrupt Line Register - ATUILR ........................................................................166
52 ATU Interrupt Pin Register - ATUIPR..........................................................................167
53 ATU Minimum Grant Register - ATUMGNT ..................................................................167