Intel CONTROLLERS 413808 - Manual (Page 13)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 13
Contents—Intel
®
413808 and 413812
7.1 Overview ....................................................................................................... 485
7.2 Theory of Operation......................................................................................... 486
7.2.1 System Controller ................................................................................ 486
7.2.2 Internal Bus Requester IDs.................................................................... 487
7.2.3 Parity Testing ...................................................................................... 488
7.3 Internal Bus Bridge.......................................................................................... 490
7.3.1 Theory of Operation.............................................................................. 490
7.3.2 Internal Bus Commands........................................................................ 491
7.3.3 Transaction Queues.............................................................................. 491
7.3.4 Bridge Memory Window......................................................................... 492
7.3.5 Ordering and Passing Rules ................................................................... 493
7.3.5.1 Strong Ordering Rule Requirements .......................................... 493
7.3.6 Parity Support ..................................................................................... 494
7.3.6.1 Address Parity Generation........................................................ 494
7.3.6.2 Address Parity Checking .......................................................... 494
7.3.6.3 Data Parity on Outbound Transactions ....................................... 494
7.3.6.4 Data Parity on Inbound Transactions ......................................... 494
7.3.7 Error Detection and Handling ................................................................. 495
7.3.7.1 Bridge North Internal Bus Interface Error................................... 495
7.3.7.2 Bridge South Internal Bus Interface Error................................... 496
7.4 System Controller Register Definitions................................................................ 497
7.5 Internal Bus Bridge Register Definitions.............................................................. 498
7.5.1 Internal Bus Arbitration Control Register — IBACR .................................... 499
7.5.2 South Internal Bus Address Test Control Register — SIBATCR .................... 501
7.5.3 South Internal Bus Data Test Control Register — SIBDTCR ........................ 502
7.5.4 Peripheral Memory-Mapped Register Base Address Register — PMMRBAR..... 503
7.5.5 Determining Block Sizes for Memory Windows.......................................... 504
7.5.6 Bridge Window Base Address Register — BWBAR...................................... 505
7.5.7 Bridge Window Upper Base Address Register — BWUBAR........................... 506
7.5.8 Bridge Window Limit Register — BWLR.................................................... 507
7.5.9 Bridge Error Control and Status Register — BECSR ................................... 508
7.5.10 Bridge Error Address Register — BERAR .................................................. 510
7.5.11 Bridge Error Upper Address Register — BERUAR ....................................... 510
8.0 SRAM Memory Controller........................................................................................... 511
8.1 Overview ....................................................................................................... 511
8.2 Glossary ........................................................................................................ 512
8.3 Theory of Operation......................................................................................... 513
8.3.1 Functional Block................................................................................... 513
8.3.1.1 North Internal Bus Ports .......................................................... 513
8.3.1.2 Address Decode Blocks............................................................ 514
8.3.1.2.1 SRAM Memory Array Space .............................................514
8.3.1.2.2 Memory-Mapped Register Space......................................514
8.3.1.2.3 North Internal Bus Port Address Decode .......................... 514
8.3.1.3 Memory Transaction Queues .................................................... 514
8.3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ) .....514
8.3.1.4 Configuration Registers............................................................ 514
8.3.1.5 SRAM Control Block................................................................. 514
8.3.1.5.1 SRAM State Machine and Pipeline Queues...................... 514
8.3.1.5.2 Error Correction Logic ....................................................... 515
8.3.1.6 North Internal Bus Port Transaction Ordering.............................. 516
8.3.1.7 SMCU Port Coherency.............................................................. 516
8.3.2 SRAM Memory Interface Support............................................................ 517
8.3.2.1 SRAM Initialization.................................................................. 517
8.3.2.2 SRAM Read Sequence.............................................................. 517
8.3.2.3 SRAM Write Sequence ............................................................. 518