Intel CONTROLLERS 413808 - Manual (Page 596)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
596 Order Number: 317805-001US
10.7.12 Interrupt Control Register 3 — INTCTL3
The Interrupt Control register 3 is a 32-bit Coprocessor 6 control register used to
specify which of 32 interrupts are masked.
Table 394. Interrupt Control Register 3 — INTCTL3 (Sheet 1 of 2)
Bit Default Description
31 1
2
HPI Interrupt Pending
0 = Masked
1 = Not Masked
30:18 0000H Reserved.
17 0
2
Inbound MSI Interrupt Pending
0 = Masked
1 = Not Masked
16 0
2
Reserved.
15 0
2
MU MSI-X Table Write Interrupt Pending
0 = Masked
1 = Not Masked
14 0
2
ATUE Interrupt Message D Pending.
0 = Masked
1 = Not Masked
13 0
2
ATUE Interrupt Message C Pending.
0 = Masked
1 = Not Masked
12 0
2
ATUE Interrupt Message B Pending.
0 = Masked
1 = Not Masked
11 0
2
ATUE Interrupt Message A Pending.
0 = Masked
1 = Not Masked
10:08 0
2
Reserved.
07 0
2
TPMI 0 Outbound Interrupt Pending.
06:05 0
2
Reserved.
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 4, Register 3