2 internal bus commands, Table 332. bridge supported internal bus commands, 3 transaction queues – Intel CONTROLLERS 413808 User Manual
Page 491: 332 bridge supported internal bus commands
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
491
System Controller (SC) and Internal Bus Bridge—Intel
®
413808 and 413812
7.3.2
Internal Bus Commands
lists the internal bus commands that are supported on the north and south
bridge interfaces.
7.3.3
Transaction Queues
Both the north and south interfaces of the bridge support a read queue of 8 entries and
each supporting up to 32 Bytes of data buffers. Both interfaces support a write queue
of 8 entries, each supporting up to 32 Bytes of data buffers.
Note:
The bridge master-aborts any transaction request that tries to cross a 32-byte
boundary. Since each data buffer is 32 bytes in size, the bridge can only transfer a
maximum byte-count of 32 bytes of data per request and only when the address is
aligned on a 32-byte boundary. In other words, for a non 32-byte aligned address, the
sum of the non-aligned address and byte-count has to be less than the next 32-byte
aligned address boundary for the bridge to enqueue the request.
Table 332. Bridge supported Internal Bus Commands
Internal Bus
Command
Encoding
Internal Bus
Command Type Claimed on North
Internal Bus
Generated on
South Internal
Bus
Claimed on South
Internal Bus
Generated on
North Internal
Bus
0000
NULL
No
Yes
No
Yes
0001
Sync
No
No
No
No
0010
Special
No
No
No
No
0011
Reserved
No
No
No
No
0100
Reserved
No
No
No
No
0101
Reserved
No
No
No
No
0110
Reserved
No
No
No
No
0111
Reserved for TLBIE No
No
No
No
1000
Read
Yes
Yes
Yes
Yes
1001
Read Line
Yes
Yes
Yes
Yes
1010
Reserved for
Invalidate Line
No
No
No
No
1011
Read and Invalidate
Line
Yes
Yes
Yes
Yes
1100
Write
Yes
Yes
Yes
Yes
1101
Reserved for Clean
and Invalidate Line No
No
No
No
1110
Write Line
Yes
Yes
Yes
Yes
1111
Reserved for Clean
Line
No
No
No
No