Intel CONTROLLERS 413808 - Manual (Page 751)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 751
PMON Unit—Intel ® 413808 and 413812
19:16 0h
Opcode
• 0000 = Stop . The corresponding counter does not count.
• 0001 = Start . The corresponding counter begins counting. Each counter increments by one when
the corresponding increment event occurs or decrements by one when the corresponding
decrement event occurs. All duration type events toggle every PMON unit clock tick that the event
is true. The desired increment and decrement events must be selected before this command
executes.
• 0010 = Sample . The corresponding counter value is latched into the corresponding data register,
which can then be read by reading the appropriate data register. The counter continues to count
without being reset. When the Condition Code is NOT False then the Data Register is not written
when a sample takes place. In other words, the Data Register is only ever updated with counter
value when the Condition Code is False.
• 0100 = Reset . The corresponding counter is reset to 0000 0000h and stops counting. The 32 bit
wide counter allows 4 billion clock ticks or occurrences to be counted between sample commands.
When the counter rolls over, the overflow status bit is set in the corresponding status register.
• 0101 = Restart . The corresponding counter resets, then starts counting again. This is essentially
a Reset & Start command. This functionality facilitates generating histograms by allowing an event
to trigger to clear the counter and resume counting with no further intervention.
• 0110 = Sample & Restart . The Sample command happens and is followed immediately by the
Restart command.
• 1111 = Preload . The corresponding counter is set to the value that is located in the associated
data register. This facilitates rollover and overflow validation. The counter remains in the same
state when preloaded. When the counter was counting before the preload was executed it
continues to count after the preload. It is software’ s responsibility to ensure that the counter is in
the desired state (example: execute stop command) prior to issuing a preload command.
All others reserved.
15 0b Reserved
Table 492. PMON Command Register 0-7 - PMON_CMD[0:7] (Sheet 3 of 4)
Bit Default Description
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
PMON _CMD0
PMON _CMD1
PMON _CMD2
PMON _CMD3
PMON _CMD4
PMON _CMD5
PMON _CMD6
PMON _CMD7
+000h
+010h
+020h
+030h
+040h
+050h
+060h
+070h