Intel CONTROLLERS 413808 - Manual (Page 511)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 511
SRAM Memory Controller—Intel
®
413808 and 413812
8.0 SRAM Memory Controller
This chapter describes the integrated SRAM Memory Controller Unit (SMCU). The
operating modes, initialization, and implementation are detailed in this chapter.
8.1 Overview
The Intel
®
413808 and 413812 I/O Controllers in TPER Mode (4138xx integrates a high
performance, multi-ported SRAM Memory Controller to provide access to the on-chip
1.0 MByte SRAM Memory. The SRAM Memory Controller supports:
• 1.0 MByte SRAM Memory
• Dedicated port for Intel XScale
®
processor to the SRAM
• Optimized core processor data processing 32-bit region.
• Single-bit error correction, multi-bit detection support (ECC)
• 256-bit wide SRAM Memory Interface
• 128-bit wide port with data parity protection
• ECC supported on 32-bit data width
The SRAM interface provides a direct connection to a high bandwidth and reliable
memory subsystem. An 7-bit Error Correction Code (ECC) across every 32-bit word
improves system reliability. The ECC is stored into the SRAM array along with the 32-bit
data and is checked when the data is read. If the code is incorrect, the SMCU corrects
the data (if possible) before reaching the initiator of the read. User-defined fault
correction software is responsible for scrubbing the memory array.
• The SMCU responds to the north internal bus, memory accesses within its
programmed address range and issues the memory request to the SRAM interface.
• The SMCU contains transaction queues for the north internal bus port enabling
pipelining of transactions to the SRAM for maximum performance.
• ECC implemented on 32-bit data for higher core write performance core by
avoiding Read-Modify-Write (RMW) operation to the SRAM.