Intel CONTROLLERS 413808 - Manual (Page 76)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
76 Order Number: 317805-001US
2.2.5.2 PCI-X Mode 2 Considerations for Outbound Configuration Cycles
In addition to the PCI-X Mode 1 changes relative to Conventional PCI mode, for PCI-X
Mode 2, the definition for bits 31:24 of the configuration address has changed. Bits
31:28 are Reserved while bits 27:24 represent the enhanced configuration cycle upper
register address providing up to 4 Kbytes of configuration register space. In addition, a
consequence of this change is that Device Numbers 15:8 are not longer available. For
Mode 2 implementations, the System hardware is restricted to Device Numbers 7:0.
Software needs to read the PCSR to confirm that the PCI interface is operating in Mode
2 in order to set bits 27:24 properly.
2.2.5.3 Outbound Configuration Cycle Error Conditions
Master aborts during outbound configuration reads result in ATU aborting the read
completion the on internal bus.
Target aborts during outbound configuration reads result in ATU aborting the read
completion on the internal bus.
Uncorrectable errors during outbound configuration reads result in ATU aborting the
read completion on the internal bus.
Uncorrectable errors detected by target of an outbound configuration write may result
in the ATU receiving either of the two Split Completion Write Uncorrectable Data Error
Messages (with message class=2h -completer error and message index=01h - split
write uncorrectable data error or with message class=1h - bridge error and message
index=02h - write uncorrectable data error) on the PCI bus. When Parity Checking is
enabled, the ATU sets error bits in the ATUSR and the PCIXSR. The Intel XScale
®
processor is interrupted when the Split Completion Error and/or Master Data Parity
interrupt(s) are unmasked.