Intel CONTROLLERS 413808 - Manual (Page 796)

Intel ® 413808 and 413812—Peripheral Registers
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
796 Order Number: 317805-001US
19.5 Default Memory Space Setup
Figure 124 shows the Intel XScale
®
processor address space and addresses available to
the applications. Figure 124 also shows the default locations of certain resources after
reset.
The PMMR Block occupies 512 KBytes of space and is located at addresses
0 FFD8 0000H through 0 FFDF FFFFH. Do not change the default address of the PMMR
block.
The Messaging Unit occupies 8 KBytes of space and is located at addresses 0 FF00
0000H through 0 FF00 1FFFH.
The ATU-X Outbound I/O Translation Window occupies 64 KBytes of space and is
located at addresses 0 FFFB 0000H through 0 FFFB FFFFH.
The ATU-E Outbound I/O Translation Window occupies 64 KBytes of space and is
located at addresses 0 FFFD 0000H through 0 FFFD FFFFH.
For a full description of the address space for the Intel XScale
®
processor Reset and
Exception Vectors, refer to the ARM Architecture Reference Manual.