Intel CONTROLLERS 413808 - Manual (Page 290)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
290 Order Number: 317805-001US
3.17.1 Extended Capabilities Registers
The ATU unit includes 5 extended capability configuration spaces beginning at
configuration offset 90H, 98H, A0H, B0H, and D0H. The extended configuration spaces
can be accessed by a device on the PCI interface through a mechanism defined in the
PCI Express Specification.
In the ATU Status Register (
Section 3.17.6 ) the appropriate bit is set indicating that the
Extended Capability Configuration space is supported. When this bit is read, the device
can then read the Capabilities Pointer register ( Section 3.17.23 ) to determine the
configuration offset of the Extended Capabilities Configuration Header. The format of
these headers are depicted in Figure 33 , Figure 35 , Figure 36 and Figure 37 .
.
The first byte at the Extended Configuration Offset 98H is the ATU Capability Identifier
Register for the PCI Bus Power Management Interface Specification, Revision 1.1.
Following the Capability Identifier Register is the single byte Next Item Pointer Register
( Section 3.17.51, “PM Next Item Pointer Register - PM_Next_Item_Ptr” on page 337 )
which indicates the configuration offset of an additional Extended Capabilities Header,
when supported. In the ATU, the Next Item Pointer Register is set to D0H indicating
that there is an additional Extended Capabilities Headers supported in the ATUs
configuration space.
To enable the PCI Bus Power Management Interface Specification, Revision 1.1
compliance support, the Power State Transition interrupt mask in bit 8 of the ATUIMR
needs to be cleared. It is the configuration software’s responsibility to properly enable
and initialize the ATUs Power Management Interface before the Configuration Cycle
Retry Bit in the Section 3.17.41, “PCI Configuration and Status Register - PCSR” on
page 327 is cleared in order for the ATU to be Advanced Configuration and Power
Interface Specification, Revision 2.0 compliant.
Note: MSI-X Capability Registers are defined in Chapter 4.0, “Messaging Unit.”
The first byte at the Extended Configuration Offset B0H is the MSI-X Capability
Identifier Register ( Section 4.7.26, “MSI-X Capability Identifier Register -
MSI-X_Cap_ID” ). This identifies this Extended Configuration Header space as the type
defined by the PCI Local Bus Specification, Revision 2.3.
Following the Capability Identifier Register is the single byte Next Item Pointer Register
( Section 4.7.27, “MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr” ) which
indicates the configuration offset of an additional Extended Capabilities Header, when
supported. In the ATU, the Next Item Pointer Register is set to A0H indicating that
there is an additional Extended Capabilities Headers supported in the ATUs
configuration space.
Figure 33. ATU Interface Extended Configuration Header Format (Power Management)
98H
9CH
Capability Identifier Next Item Pointer Power Management Capabilities
Power Management Control/Status Reserved
Figure 34. ATU Interface Extended Configuration Header Format (MSI-X Capability)
B0H
B4H
MSI-X Capability ID MSI-X Next Item Pointer MSI-X Message Control
MSI-X Table Offset
MSI-X PBA Offset B8H
Table BIR
PBA BIR