5 uart x fifo control register, 452 uart x fifo control register - (uxfcr) – Intel CONTROLLERS 413808 User Manual
Page 674
Intel
®
413808 and 413812—UARTs
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
674
Order Number: 317805-001US
13.4.5
UART x FIFO Control Register
FCR is a write only register that is located at the same address as the IIR (IIR is a read
only register). FCR enables/disables the transmitter/receiver FIFOs, clears the
transmitter/receiver FIFOs, and sets the receiver FIFO trigger level.
Table 452. UART x FIFO Control Register - (UxFCR) (Sheet 1 of 2)
Bit
Default
Description
31:8
00 0000h
Reserved
7:6
00
2
Interrupt Trigger Level (ITL): When the number of bytes in the receiver FIFO
equals the interrupt trigger level programmed into this field and the Received Data
Available Interrupt is enabled (via IER), an interrupt is generated and appropriate
bits are set in the IIR.
00 = 1 byte or more in FIFO causes interrupt
01 = 8 bytes or more in FIFO causes interrupt
10 = 16 bytes or more in FIFO causes interrupt
11 = 32 bytes or more in FIFO causes interrupt
5:4
0
2
Preserved
3
0
2
Transmitter Interrupt Level (TIL): Setting TIL causes Transmitter Interrupts to
occur when the Transmit FIFO is empty. Clearing TIL causes Transmitter Interrupts
to occur when the Transmit FIFO is half empty.
0 = Interrupt when FIFO is half empty
1 = Interrupt when FIFO is empty
PC
I
IO
P
A
tt
ri
bu
te
s
A
tt
ri
bu
te
s
28
24
20
16
12
8
4
0
31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
wo
na
wo
na
pr
na
pr
na
wo
na
wo
na
wo
na
wo
na
Unit #
01
Intel XScale
®
Core internal bus address
+2308H (DLAB=x)
+2348H (DLAB=x)
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible