Intel CONTROLLERS 413808 - Manual (Page 690)

Intel ® 413808 and 413812—I 2 C Bus Interface Units
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
690 Order Number: 317805-001US
14.2 Theory of Operation
The I
2
C bus defines a serial protocol for passing information between agents on the I
2
C
bus, using only a two pin interface. The interface consists of a Serial Data/Address
( SDA ) line and a Serial Clock Line ( SCL ). Each device on the I
2
C bus is recognized by a
unique 7-bit address and can operate as a transmitter or as a receiver. In addition to
transmitter and receiver, the I
2
C bus uses the concept of master and slave. Table 464
lists the I
2
C device types.
As an example of I
2
C bus operation, consider the case of the 4138xx acting as a master
on the bus ( Figure 91 ). The 4138xx, as a master, addresses an EEPROM as a slave to
receive data. The 4138xx is a master-transmitter and the EEPROM is a slave-receiver.
When the 4138xx reads data, the 4138xx is a master-receiver and the EEPROM is a
slave-transmitter. In both cases, the master generates the clock, initiates the
transaction and terminates it.
Table 464. I
2
C Bus Definitions
I
2
C Device Definition
Transmitter Sends data to the I 2 C bus.
Receiver Receives data from the I 2 C bus.
Master Initiates a transfer, generates the clock signal, and terminates the transactions.
Slave The device addressed by a master.
Multi-master
More than one master can attempt to control the bus at the same time without corrupting
the message.
Arbitration
Procedure to ensure that, when more than one master simultaneously tries to control the
bus, only one is allowed. This procedure ensures that messages are not corrupted.
Figure 91. I
2
C Bus Configuration Example
Microcontroller
Gate
Array
EEPROM
SCL
SDA
Intel® I/O
Processor
B6282-01