12 central resource functionality, 1 multi-function support, 2 outbound transactions – Intel CONTROLLERS 413808 User Manual

Page 132: 3 pci reset (p_rstout#), 4 pci clock outputs (p_clkout, p_clko[3:0]), 3 pci reset, 4 pci clock outputs

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Intel

®

413808 and 413812—Address Translation Unit (PCI-X)

Intel

®

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

132

Order Number: 317805-001US

2.12

Central Resource Functionality

Central Resource is not supported on 4138xx.

2.12.1

Multi-Function Support

When operating as a central resource, the ATU behaves as a single function device and

claims memory transactions only for the ATU function. This means that the BARs and

control signals from other internal functions are ignored, and any PCI status updates

are limited to the ATU.

2.12.2

Outbound Transactions

ATU outbound transaction support is detailed in

Section 2.2.2, “Outbound Transactions-

Single Address Cycle (SAC) Internal Bus Transactions”

. The behavior is the same in

both end point and central resource modes of operation.

2.12.3

PCI Reset (P_RSTOUT#)

When the Central Resource is enabled (

PCIX_EP#

= 1), the ATU controls generation of

P_RSTOUT#

for the PCI Bus segment attached to the ATU.

The ATU controls the PCI Reset signal (

P_RSTOUT#

) for the external agents supported

by the 4138xx Central Resource. When the Central Resource is enabled,

P_RSTOUT#

remains asserted following the deassertion of the fundamental reset.

P_RSTOUT#

can

be deasserted in the

“PCI Configuration and Status Register - PCSR” on page 178

.

2.12.4

PCI Clock Outputs (P_CLKOUT, P_CLKO[3:0])

The

P_CLKOUT

/

P_CLKO[3:0]

PCI clock outputs are available when operating in

central resource mode and the primary clock source is the PCI Express* reference clock

(

CLK_SRC_PCIE#

= 0). In this operating mode, the

P_CLKOUT

signal is connected

to the

P_CLKIN

pin and trace match to the

P_CLKO[3:0]

signals.

Warning:

When the

P_CLKIN

is the primary clock source (

CLK_SRC_PCIE#

= 1), the PCI Clock

outputs are disabled and cannot be used as a clock source for any device.

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