Intel CONTROLLERS 413808 - Manual (Page 287)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 287
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.14.2 PCI Express Interface Status Reporting
The following registers are located in the configuration space header and extended
space and provide status (error conditions) of the PCI Express Interface.
Table 139. PCI Express Interface Status Reporting Usage
a
a. This table is referring to only enabled functions. And in root complex mode multi-function is not applicable.
Register Name Register Bits Description Usage
ATU Status Register - ATUSR
Bit 15 - Detected Parity Error Poisoned TLP received is reported in
the function involved.
Bit 14 - SERR# Asserted
SERR# Asserted is reported in the
function involved.
Bit 13 - Master Abort
Received Unsupported Request
Completion is reported in the
function involved.
Bit 12 - Received Target
Abort
Received Completer Abort
Completion is reported in the
function involved.
Bit 11 - Signaled Target
Abort
Transmitted Completer Abort
Completion is reported in the
function involved.
Bit 8 - Bit Master Parity Error Master Parity Error is reported to
only the function involved.
PCI Express Device Status Register
PE_DSTS
Entire Register Reported per function.
PCI Express Link Status Register
PE_LSTS
Entire Register Reported per function.
PCI Express Uncorrectable Error Status
- ERRUNC_STS
Entire Register Reported per function
PCI Express Correctable Error Status -
ERRCOR_STS
Entire Register Reported per function
PCI Express Advanced Error Header
Log - ADVERR_LOG0
Entire Register Reported per function
PCI Express Advanced Error Header
Log - ADVERR_LOG1
Entire Register Reported per function
PCI Express Advanced Error Header
Log - ADVERR_LOG2
Entire Register Reported per function
PCI Express Advanced Error Header
Log - ADVERR_LOG3
Entire Register Reported per function