Intel CONTROLLERS 413808 - Manual (Page 427)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 427
Messaging Unit—Intel
®
413808 and 413812
4.7.17 MU MSI-X Table Message Data Registers - M_MT_MDR[0:7]
The MU MSI-X Table Message Data Register contains the message data of the MSI-X
message. An entry in the MSI-X Table is made up of four DWORDs.
Note: The M_MT_MDR[0:7] registers are not reset with an internal bus reset.
Table 282. MU MSI-X Table Message Upper Address Registers - M_MT_MUAR [0:7]
Bit Default Description
31:00 0000 0000H Message Data: This field contains the message data for this Table entry.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
M_MT_MAR0
M_MT_MAR1
M_MT_MAR2
M_MT_MAR3
M_MT_MAR4
M_MT_MAR5
M_MT_MAR6
M_MT_MAR7
internal bus address
offset
5008H
5018H
5028H
5038H
5048H
5058H
5068H
5078H
M_MT_MAR0
M_MT_MAR1
M_MT_MAR2
M_MT_MAR3
M_MT_MAR4
M_MT_MAR5
M_MT_MAR6
M_MT_MAR7
MU/PCI Base Address
Offset
1008H
1018H
1028H
1038H
1048H
1058H
1068H
1078H