68 pci express root status register - pe_rsr, Table 208. pci express root status register pe_rsr, 68pci express root status register - pe_rsr – Intel CONTROLLERS 413808 User Manual

Page 354: 208 pci express root status register pe_rsr, Pci express root status, Intel, Bit default description

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Intel

®

413808 and 413812—Address Translation Unit (PCI Express)

Intel

®

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

354

Order Number: 317805-001US

3.17.68 PCI Express Root Status Register - PE_RSR

The Root Statue Register provides information about PCI Express device specific

parameters.

3.17.69 PCI Express Advanced Error Capability Identifier -

ADVERR_CAPID

This register stores the PCI Express extended capability ID value.

Table 208. PCI Express Root Status Register PE_RSR

Bit

Default

Description

31:18

0000H

Reserved Zero - Software must write 0 to these bits

17

0

PME Pending: The read-only bit indicates that another PME is pending when the PME Status bit is set.

When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME

Status bit again and updating the Requester ID appropriately.

The ATU only supports a single PME at a time. This bit hard-wired to 0.

16

0

PME Status: This bit indicate that PME was asserted by the requestor ID indicated in the PME requestor

ID field.

Subsequent PMEs are dropped until the status register is cleared by software by writing a 1 to this bit.

15:0

0000H

PME Requestor ID

This field indicates the PCI requestor ID of the first PME requestor.

PCI

IOP

Attributes

Attributes

28

24

20

16

12

8

4

0

31

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

rz

ro

ro

rc

rc

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

Attribute Legend:

RZ = Reserved Zero

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+0F0H

Table 209. PCI Express Advanced Error Capability Identifier - ADVERR_CAPID

Bit

Default

Description

31:20

000H

Next PCI Express Extended Capability Pointer: This is the last capability. Program with 1E0H to point to

the PCI Express Device Serial Number as the next capability, or program with 1F0H to bypass the DSN

and point to Power Budgeting as the next capability.

19:16

1H

Advanced Error Capability Version Number: PCI Express Advanced Error Reporting Extended Capability

Version Number.

15:0

0001H

Advanced Error Capability ID: PCI Express Extended Capability ID indicating Advanced Error Reporting

Capability.

PCI

IOP

Attributes

Attributes

28

24

20

16

12

8

4

0

31

rw

ro

rw

ro

rw

ro

rw

ro

rw

ro

rw

ro

rw

ro

rw

ro

rw

ro

rw

ro

rw

ro

rw

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

ro

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+100H

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