9 sram parity address register - spar, Table 358. sram parity address registers - spar, 10 sram parity upper address register - spuar – Intel CONTROLLERS 413808 User Manual

Page 543: 9 sram parity address register — spar, 10 sram parity upper address register — spuar, 358 sram parity address registers — spar, 359 sram parity upper address register — spuar, Table 358. sram parity address registers — spar, Bit default description, Reserved

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Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

543

SRAM Memory Controller—Intel

413808 and 413812

8.6.9

SRAM Parity Address Register — SPAR

This register is responsible for logging the lower 32-bit address of where the error was

detected on the SMCU memory ports. Note that the address is 36-bit. This register is

used in conjunction with the

Section 8.6.10, “SRAM Parity Upper Address Register —

SPUAR” on page 543

. One error can be detected and logged. The software knows which

SRAM address had the error by reading this register and decoding contents of

associated log register. For error details, see

Section 8.3.3, “Error Correction and

Detection” on page 519

8.6.10

SRAM Parity Upper Address Register — SPUAR

This register is responsible for logging the upper 4-bit address of where the error was

detected on the SMCU memory ports. Note that the address is 36-bit. This register is

used in conjunction with the

Section 8.6.9, “SRAM Parity Address Register — SPAR” on

page 543

. One error can be detected and logged. The software knows which SRAM

address had the error by reading this register and decoding contents of associated log

Section 8.3.4, “Byte Parity Checking and Generation” on

page 528

Table 358. SRAM Parity Address Registers — SPAR

Bit

Default

Description

31:02

0000 0000H

Error Address: Stores the upper 30 bits of the address that resulted in a parity error.

01:00

Reserved

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Intel XScale

processor Local Bus Address Offset

+1520H

Table 359. SRAM Parity Upper Address Register — SPUAR

Bit

Default

Description

31:04

0000 000H

Reserved

03:00

0000

Parity Error Address: Stores the upper 4 bits of the 36-bit address that resulted in the parity error.

PCI

IOP