Intel CONTROLLERS 413808 - Manual (Page 732)

Intel ® 413808 and 413812—PMON Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
732 Order Number: 317805-001US
16.4 Data Collection
The following sections provide some insight into the intended use of the PMON
counters at a very low level. The examples and accompanying explanation should prove
especially valuable in the creation of test cases for both hardware and software.
The hardware face to the
PMON counters is not intended to be any wider than 32 bits.
This means that all registers are accessed one at a time.
All of the following examples assume starting with an idle system (all counters stopped
and all registers set to default values). The waveforms in the examples do not explicitly
always show when each PMON command was executed, but the reader should be able
to deduce when each command would have or could have executed. For the purposes
of these examples, the waveforms treat the counters as being level sensitive to the
appropriate events.
16.4.1 Time Based Sampling
Figure 109. Flowchart of Example Commands Sequence
B6299-01