Intel CONTROLLERS 413808 - Manual (Page 775)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 775
Clocking and Reset—Intel ® 413808 and 413812
When the reset internal bus bit in the PCI Configuration and Status Register is set,
there are sideband signals notifying the ATUX and MCU that a reset is coming.
Table 514, “Internal Bus Reset Summary” describes the operation of each unit:
Table 513. Internal Bus Reset Control Bit Locations
Unit Coordinated Reset Selective Reset
MU IRCSR[1] IRSCR[0]
Table 514. Internal Bus Reset Summary (Sheet 1 of 2)
Unit Preparation for Reset Reset Status
ATUX
The affect on the ATUX depends on the PCIX_EP# strap.
End Point Mode ( PCIX_EP# = 0):
When the ATUX is informed that an internal bus reset is
coming it does the following:
PCI Interface Outbound Transaction:
• When the ATUX has already asserted its PCI request
signal, and not yet started a transaction, the ATUX
deasserts its request and not start its transaction.
• When the ATUX has not yet requested the PCI bus, the
ATUX never asserts its request for the PCI bus.
• When the ATUX is in the middle of a transaction, the
ATUX performs the existing transaction. This means that
an inbound write, the ATUX transfers as much data as
available in the queue. When an outbound read, the
ATUX reads the data until the transaction stops naturally
(meaning that the target has ended the transaction or
the ATUX has read all of the data it has been requested
to read). Once terminated by the ATUX or the target, the
ATUX no longer requests the PCI bus.
• In PCI-X mode, the ATUX allows any outstanding split
completions due to prior outstanding Split Requests to
Master-Abort on the PCI Bus. Since, the IOP is only
accessing Prefetchable Memory on the host, no error
condition is created in the system.
PCI Interface Inbound Transaction:
• The ATUX no longer claims any new transactions on the
PCI bus. This results in a master abort to the initiating
master.
• In PCI-X mode, data from an outstanding split request
may not be returned to the host. It is the responsibility
of the host software to handle this condition as a
consequence of writing to the Internal Bus Reset bit.
Internal Bus Interface: Inbound Transaction:
• The ATUX goes ahead and assert their IB request
signals, and try to continue any pending transactions as
normal. There are no special actions taken on the
internal bus for inbound transactions.
Internal Bus Interface: Outbound Transaction:
• For all ATUX outbound transactions, there are no special
requirements since the internal units are reset.
Upon meeting both the outbound and inbound transaction
requirements, the ATUX asserts the sideband signal to the
reset unit notifying it is ready-for-reset.
Central Resource Mode ( PCIX_EP# = 1)
No special requirements, the ATUX can be reset at anytime.
This reset includes the configuration space.
End Point Mode:
Clear all ATUX queues and state
machines.
All ATUX Configuration Registers
retain their current values.
Central Resource Mode:
Entire ATUX is reset, including
Configuration Registers.