7 pbi limit register 1 - pblr1, Table 370. pbi limit register 1 - pblr1, 7 pbi limit register 1 — pblr1 – Intel CONTROLLERS 413808 User Manual
Page 560: 370 pbi limit register 1 — pblr1, Intel, Bit default description, Processor local bus address, 1594h
Intel
®
413808 and 413812—Peripheral Bus Interface Unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
560
Order Number: 317805-001US
9.3.7
PBI Limit Register 1 — PBLR1
The 4138xx limit register (PBLR1) and base address register (PBBAR1) programmed
values must be naturally aligned. The limit register is used as a mask when the address
decode for memory window 1 is performed.
.
Table 370. PBI Limit Register 1 — PBLR1
Bit
Default
Description
31:12
00000H
Memory Window 1 Limit: Determines the memory block size required for the Memory Window 1.
11:00
000H
Reserved
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale
®
processor Local Bus Address
Offset
+1594H